HD6417641 RENESAS [Renesas Technology Corp], HD6417641 Datasheet - Page 492

• Manufacturer Part Number: HD6417641
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 13 Direct Memory Access Controller (DMAC)
Figure 13.17 shows the TEND output timing.
Rev. 4.00 Sep. 14, 2005 Page 442 of 982
REJ09B0023-0400
Figure 13.16 Example of DREQ Input Detection in Burst Mode Level Detection
Figure 13.17 Example of DREQ Input Detection in Burst Mode Level Detection
CKIO
Bus cycle
DREQ
DACK
TEND
CKIO
CKIO
Bus cycle
DREQ
(Rising)
DACK
(Active-high)
Bus cycle
DREQ
(Overrun 1 at
high level)
DACK
(Active-high)
DMAC
1st acceptance
1st acceptance
CPU
CPU
Non sensitive period
Non sensitive period
CPU
CPU
CPU
End of DMA transfer
DMAC
2nd acceptance
DMAC
DMAC
Acceptance
start
CPU
2nd acceptance
Acceptance
start
3rd
acceptance
DMAC
Acceptance
start
CPU