HD6417641 RENESAS [Renesas Technology Corp], HD6417641 Datasheet - Page 359

• Manufacturer Part Number: HD6417641
• Manufacturer: RENESAS [Renesas Technology Corp]

Note:
Burst MPX-IO:
• CS6BWCR
Bit
2
1
0
Bit
31 to 22
21
20
*
Bit Name

MPXAW1
MPXAW0
If both areas 2 and 3 are specified as SDRAM, WTRP[1:0], WTRCD[1:0], TRWL[1:0],
and WTRC[1:0] bit settings are common. If only one area is connected to the SDRAM,
specify area 3. In this case, specify area 2 as normal space or byte-selection SRAM.
Bit Name

WTRC1*
WTRC0
Initial
Value
0
0
0
Initial
Value
All 0
0
0
R/W
R/W
R
R/W
R/W
R
R/W
R/W
Description
Reserved
This bit is always read as 0. The write value should
always be 0.
Number of Idle Cycles from REF Command/Self-
Refresh Release to ACTV/REF/MRS Command
Specify the number of minimum idle cycles during the
periods shown below.
•
•
The setting for areas 2 and 3 is common.
00: 2 cycles (Initial value)
01: 3 cycles
10: 5 cycles
11: 8 cycles
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Number of Address Cycle Waits
Specify the number of waits to be inserted in the
address cycle.
00: No cycle
01: 1 cycle
10: 2 cycles
11: 3 cycles
From issuing of the REF command to issuing of the
ACTV/REF/MRS command
From releasing self-refresh to issuing of the
ACTV/REF/MRS command
Rev. 4.00 Sep. 14, 2005 Page 309 of 982
Section 12 Bus State Controller (BSC)
REJ09B0023-0400