HD6417641 RENESAS [Renesas Technology Corp], HD6417641 Datasheet - Page 523

• Manufacturer Part Number: HD6417641
• Manufacturer: RENESAS [Renesas Technology Corp]

The I
interface functions. However, the configuration of the registers that control the I
partly from the Philips register configuration.
Figure 16.1 shows a block diagram of the I
I/O pin connections to external circuits.
16.1
• Selection of I
• Continuous transmission/reception
I
• Start and stop conditions generated automatically in master mode
• Selection of acknowledge output levels when receiving
• Automatic loading of acknowledge bit when transmitting
• Bit synchronization/wait function
• Six interrupt sources
• Direct bus drive
Clocked synchronous format:
• Four interrupt sources
2
C bus format:
Since the shift register, transmit data register, and receive data register are independent from
each other, the continuous transmission/reception can be performed.
In master mode, the state of SCL is monitored per bit, and the timing is synchronized
automatically.
If transmission/reception is not yet possible, set the SCL to low until preparations are
completed.
Transmit data empty (including slave-address match), transmit end, receive data full (including
slave-address match), arbitration lost, NACK detection, and stop condition detection
Two pins, SCL and SDA pins, function as NMOS open-drain outputs when the bus drive
function is selected.
Transmit-data-empty, transmit-end, receive-data-full, and overrun error
2
C bus interface 2 conforms to and provides a subset of the Philips I
Features
2
C format or clocked synchronous serial format
Section 16 I
2
C Bus Interface 2 (IIC2)
2
C bus interface 2. Figure 16.2 shows an example of
Rev. 4.00 Sep. 14, 2005 Page 473 of 982
Section 16 I
2
C (Inter-IC) bus
2
C Bus Interface 2 (IIC2)
2
C bus differs
REJ09B0023-0400