HD6417641 RENESAS [Renesas Technology Corp], HD6417641 Datasheet - Page 997

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HD6417641

Manufacturer Part Number
HD6417641
Description
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
(Bank Active Mode: WRITE Command, Same Row Address, WTRCD = 0 Cycle,
Figure 25.35 Synchronous DRAM Burst Write Bus Cycle (Four Write Cycles)
A12/A11*
D31 to D0
A25 to A0
DACKn*
RASU/L
CASU/L
RD/WR
DQMxx
CKIO
CKE
CSn
BS
1
2
Note:
1. An address pin to be connected to pin A10 of SDRAM.
2. Waveform for DACKn when active low is selected.
t
t
t
DQMD1
t
RWD1
t
CSD1
AD1
DACD
Tnop
t
TRWL = 0 Cycle)
t
t
RWD1
t
AD1
AD1
t
WDD2
CASD1
t
BSD
Tc1
t
t
AD1
WDH2
Tc2
address
Column
(High)
Write command
t
AD1
Rev. 4.00 Sep. 14, 2005 Page 947 of 982
Tc3
Section 25 Electrical Characteristics
t
AD1
t
WDD2
Tc4
t
t
t
DQMD1
t
AD1
t
AD1
t
t
t
DACD
CASD1
WDH2
BSD
t
RWD1
CSD1
REJ09B0023-0400

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