HD6417641 RENESAS [Renesas Technology Corp], HD6417641 Datasheet - Page 254

• Manufacturer Part Number: HD6417641
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 9 Exception Handling
Table 9.1
Notes: 1. Priorities are indicated from high to low, 1 being the highest and 3 the lowest.
Rev. 4.00 Sep. 14, 2005 Page 204 of 982
REJ09B0023-0400
Exception
Type
Reset
General
exception
events
General
exception
events
General
interrupt
requests
2. For details on priorities in multiple interrupt sources, refer to section 10, Interrupt
3. If an interrupt is accepted, the exception event register (EXPEVT) is not changed. The
4. If one of these exceptions occurs in a specific part of the repeat loop, a specific code
Current
Instruction
Aborted
Re-executed
Completed
Completed
Completed
A reset has the highest priority. An interrupt is accepted only when general exceptions
are not requested.
Controller (INTC).
interrupt source code is specified in interrupt source register 2 (INTEVT2). For details,
refer to section 10, Interrupt Controller (INTC).
and vector offset are specified.
Exception Event Vectors
Exception Event
Power-on reset
Manual reset
H-UDI reset
User break
(before instruction execution)
CPU address error
(instruction access) *
Illegal general instruction exception
Illegal slot instruction exception
CPU address error (data access)*
Unconditional trap
(TRAPA instruction)
User breakpoint
(After instruction execution, address)
User breakpoint
(Data break, I-BUS break)
DMA address error
Interrupt requests
4
4
Priority*
1
1
1
2
2
2
2
2
2
2
2
2
3
1
Exception
Order
1
2
1
0
1
2
2
3
4
5
5
6
—*
2
Process
at BL=1
Reset
Reset
Reset
Ignored
Reset
Reset
Reset
Reset
Reset
Ignored
Ignored
Retained H'5C0
Retained
Vector
Code
H'A00
H'020
H'000
H'1E0
H'0E0
H'180
H'1A0
H'0E0/
H'100
H'160
H'1E0
H'1E0
—*
3
H'00000100
H'00000100
H'00000100
Vector
Offset

—
—
H'00000100
H'00000100
H'00000100
H'00000100
H'00000100
H'00000100
H'00000600