HD6417641 RENESAS [Renesas Technology Corp], HD6417641 Datasheet - Page 380

• Manufacturer Part Number: HD6417641
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 12 Bus State Controller (BSC)
When the WM bit in CSnWCR is cleared to 0, the external wait input WAIT signal is also
sampled. WAIT pin sampling is shown in figure 12.10. A 2-cycle wait is specified as a software
wait. The WAIT signal is sampled on the falling edge of CKIO at the transition from the T1 or Tw
cycle to the T2 cycle.
Rev. 4.00 Sep. 14, 2005 Page 330 of 982
REJ09B0023-0400
Read
Write
Figure 12.10 Wait State Timing for Normal Space Access
D31 to D0
D31 to D0
A25 to A0
DACKn*
RD/WR
(Wait State Insertion Using WAIT Signal)
WAIT
CKIO
WEn
CSn
RD
BS
Note: * The waveform for DACKn is when active low is specified.
T1
Tw
Tw
Twx
Wait states inserted
by WAIT signal
T2