HD6417641 RENESAS [Renesas Technology Corp], HD6417641 Datasheet - Page 995

• Manufacturer Part Number: HD6417641
• Manufacturer: RENESAS [Renesas Technology Corp]

A12/A11*
D31 to D0
A25 to A0
DACKn*
RASU/L
CASU/L
RD/WR
DQMxx
(Bank Active Mode: PRE + ACT + READ Commands, Different Row Addresses,
CKIO
Figure 25.33 Synchronous DRAM Burst Read Bus Cycle (Four Read Cycles)
CKE
CSn
BS
1
2
Note:
t
t
t
t
t
t
t
CSD1
RWD1
RASD1
DQMD1
AD1
AD1
DACD
1. An address pin to be connected to pin A10 of SDRAM.
2. Waveform for DACKn when active low is selected.
Tp
t
t
t
AD1
RWD1
RASD1
address
Trw
Row
CAS Latency 2, WTRCD = 0 Cycle)
t
RASD1
Tr
t
t
t
t
AD1
RASD1
AD1
CASD1
t
BSD
Tc1
t
AD1
Tc2
address
Column
t
AD1
Td1
(High)
Tc3
Read command
t
RDS2
Rev. 4.00 Sep. 14, 2005 Page 945 of 982
t
AD1
t
RDH2
Td2
Tc4
Section 25 Electrical Characteristics
t
CASD1
t
BSD
Td3
t
Td4
RDS2
REJ09B0023-0400
t
t
t
CSD1
t
RDH2
DQMD1
DACD
Tde
t
t
t
RWD1
AD1
AD1