HD6417641 RENESAS [Renesas Technology Corp], HD6417641 Datasheet - Page 811

• Manufacturer Part Number: HD6417641
• Manufacturer: RENESAS [Renesas Technology Corp]

20.3.19 USBFIFO Clear Register (USBFCLR)
USBFCLR is provided to initialize the FIFO buffers for each endpoint. Writing 1 to a bit clears all
the data in the corresponding FIFO buffer. The corresponding interrupt flag is not cleared. Do not
clear a FIFO buffer during transmission/reception.
USBFCLR can be initialized to H'00 by a power-on reset.
Bit
4
3 to 1
0
Bit
7
6
5
4
3, 2
1
Bit Name
EP2DE

EP0iDE
Bit Name

EP3CLR
EP1CLR
EP2CLR

EP0oCLR
Initial
Value
0
All 0
0
Initial
Value
0
0
0
0
All 0
0
R/W
R
R
R
R/W

W
W
W

W
Description
EP2 Data Present
This bit is set when the endpoint 2 FIFO buffer
contains valid data
Reserved
The write value should always be 0.
EP0i Data Present
This bit is set when the endpoint 0 transmit FIFO
buffer contains valid data.
Description
Reserved
The write value should always be 0.
EP3 Clear
When 1 is written to this bit, the endpoint 3 transmit
FIFO buffer is initialized.
EP1 Clear
When 1 is written to this bit, both FIFOs in the
endpoint 1 receive FIFO buffer are initialized.
EP2 Clear
When 1 is written to this bit, both FIFOs in the
endpoint 2 transmit FIFO buffer are initialized.
Reserved
The write value should always be 0.
EP0o Clear
When 1 is written to this bit, the endpoint 0 receive
FIFO buffer is initialized.
Rev. 4.00 Sep. 14, 2005 Page 761 of 982
Section 20 USB Function Module
REJ09B0023-0400