HD6417641 RENESAS [Renesas Technology Corp], HD6417641 Datasheet - Page 598

• Manufacturer Part Number: HD6417641
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 18 Multi-Function Timer Pulse Unit (MTU)
18.3.4
The TIER registers are 8-bit readable/writable registers that control enabling or disabling of
interrupt requests for each channel. The MTU has five TIER registers, one for each channel.
Rev. 4.00 Sep. 14, 2005 Page 548 of 982
REJ09B0023-0400
Bit
7
6
5
4
Timer Interrupt Enable Register (TIER)
Bit Name
TTGE
TGFASEL
TCIEU
TCIEV
Initial
value
0
0
0
0
R/W
R/W
R/W
R/W
R/W
A/D Conversion Start Request Enable
Description
Enables or disables generation of A/D conversion start
requests by TGRA input capture/compare match.
0: A/D conversion start request generation disabled
1: A/D conversion start request generation enabled
TGFA Interrupt/DMA Transfer Select
Selects the TGFA interrupt request or DMA transfer
request when the TGFA flag in TGRA is set to 1.
0: Interrupt request
1: DMA transfer request
Underflow Interrupt Enable
Enables or disables interrupt requests (TCIU) by the
TCFU flag when the TCFU flag in TSR is set to 1 in
channels 1 and 2.
In channels 0, 3, and 4, bit 5 is reserved. It is always
read as 0, and should only be written with 0.
0: Interrupt requests (TCIU) by TCFU disabled
1: Interrupt requests (TCIU) by TCFU enabled
Overflow Interrupt Enable
Enables or disables interrupt requests (TCIV) by the
TCFV flag when the TCFV flag in TSR is set to 1.
0: Interrupt requests (TCIV) by TCFV disabled
1: Interrupt requests (TCIV) by TCFV enabled