HD6417641 RENESAS [Renesas Technology Corp], HD6417641 Datasheet - Page 785

• Manufacturer Part Number: HD6417641
• Manufacturer: RENESAS [Renesas Technology Corp]

Figure 19.12 shows a sample flowchart for initializing the SCIF.
in SCSCR (leaving TE, RE, TIE,
Set RTRG1-0 and TTRG1-0 bits
Set TE and RE bits in SCSCR
in SCFCR, and clear TFRST
Set TFRST and RFRST bits
Set CKE1 and CKE0 bits
and RIE bits cleared to 0)
and ER flags in SCFSR,
Set data transfer format
After reading BRK, DR,
in SCFCR to 1 to clear
to 1, and set TIE, RIE,
1-bit interval elapsed?
Clear TE and RE bits
Figure 19.12 Sample Flowchart for SCIF Initialization
write 0 to clear them
and RFRST bits to 0
Set value in SCBRR
Start of initialization
End of initialization
the FIFO buffer
in SCSCR to 0
and REIE bits
in SCSMR
Yes
Wait
No
[1]
[2]
[3]
[4]
[5]
Section 19 Serial Communication Interface with FIFO (SCIF)
[1]
[2]
[3]
[4]
[5]
Leave the TE and RE bits cleared
to 0 until the initialization almost
ends. Be sure to clear the TIE,
RIE, TE, and RE bits to 0.
Set the data transfer format in
SCSMR.
Set the CKE1 and CKE0 bits.
Write a value corresponding to
the bit rate into SCBRR. This
is not necessary if an external
clock is used. Wait at least one
bit interval after this write before
moving to the next step.
Set the TE or RE bit in SCSCR
to 1. Also set the TEI, RIE, and
REIE bits to enable the TxD,
RxD, and SCK pins to be used.
When transmitting, the TxD pin
will go to the mark state.
When receiving in clocked
synchronous mode with the
synchronization clock output (clock
master) selected, a clock starts to
be output from the SCIF_CLK pin
at this point.
Rev. 4.00 Sep. 14, 2005 Page 735 of 982
REJ09B0023-0400