HD6417641 RENESAS [Renesas Technology Corp], HD6417641 Datasheet - Page 160

• Manufacturer Part Number: HD6417641
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 3 DSP Operation
In this arithmetic shift operation, all bits of the source 1 and destination operands are activated.
The shift amount is specified by the source 2 operand as an integer data. The source 2 operand can
be specified by either a register or immediate operand. The available shift range is from
–32 to +32. Here, a negative value means the right shift, and a positive value means the left shift.
It is possible for any source 2 operand to specify from –64 to +63 but the result is unknown if an
invalid shift value is specified. In case of a shift with an immediate operand instruction, the source
1 operand must be the same register as the destination's. This operation is executed in the DSP
stage, as shown in figure 3.2 as well as in fixed-point operations. The DSP stage is the same stage
as the MA stage in which memory access is performed.
Every time an arithmetic shift operation is executed, the DC, N, Z, V, and GT bits in DSR are
basically updated in accordance with the operation result. In case of a conditional operation, they
are not updated even though the specified condition is true and the operation is executed. In case
of an unconditional operation, they are always updated in accordance with the operation result.
The definition of the DC bit is selected by the CS[2:0] (condition selection) bits in DSR. The DC
bit result is:
1. Carry or Borrow Mode: CS[2:0] = 000
2. Negative Value Mode: CS[2:0] = 001
3. Zero Value Mode: CS[2:0] = 010
4. Overflow Mode: CS[2:0] = 011
5. Signed Greater Than Mode: CS[2:0] = 100
6. Signed Greater Than or Equal Mode: CS[2:0] = 101
The N bit always indicates the same state as the DC bit set in negative value mode by the CS[2:0]
bits. See the negative value mode part above. The Z bit always indicates the same state as the DC
bit set in zero value mode by the CS[2:0] bits. See the zero value mode part above. The V bit
always indicates the same state as the DC bit set in overflow mode by the CS[2:0] bits. See the
overflow mode part above. The GT bit always indicates the same state as the DC bit set in signed
greater than mode by the CS[2:0] bits. See the signed greater than mode part above.
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The DC bit indicates the last shifted out data as the operation result.
The DC bit is set when the operation result is a negative value, and cleared when the operation
result is zero or a positive value.
The DC bit is set when the operation result is zero; otherwise it is cleared.
The DC bit is always cleared.
The DC bit is always cleared.
The DC bit is always cleared.