HD6417641 RENESAS [Renesas Technology Corp], HD6417641 Datasheet - Page 351

• Manufacturer Part Number: HD6417641
• Manufacturer: RENESAS [Renesas Technology Corp]

Burst ROM (Clock Asynchronous):
• CS0WCR
Bit
1
0
Bit
31 to 21
20
19, 18
Bit Name

BEN

Bit Name
HW1
HW0
Initial
Value
All 0
0
All 0
Initial
Value
0
0
R/W
R/W
R/W
R/W
R
R/W
R
Description
Number of Delay Cycles from RD, WEn Negation to
Address, CSn Negation
Specify the number of delay cycles from RD, WEn
negation to address, and CSn negation.
00: 0.5 cycles
01: 1.5 cycles
10: 2.5 cycles
11: 3.5 cycles
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Burst Enable Specification
Enables or disables 8-burst access for a 16-bit bus
width or 16-burst access for an 8-bit bus width during
16-byte access. If this bit is set to 0, 2-burst access is
performed four times when the bus width is 16 bits and
4-burst access is performed four times when the bus
width is 8 bits. To use a device that does not support
8-burst access or 16-burst access, set this bit to 1.
0: Enables 8-burst access for a 16-bit bus width and
1: Disables 8-burst access for a 16-bit bus width and
Reserved
These bits are always read as 0. The write value
should always be 0.
16-burst access for an 8-bit bus width.
16-burst access for an 8-bit bus width.
Rev. 4.00 Sep. 14, 2005 Page 301 of 982
Section 12 Bus State Controller (BSC)
REJ09B0023-0400