HD6417641 RENESAS [Renesas Technology Corp], HD6417641 Datasheet - Page 497

• Manufacturer Part Number: HD6417641
• Manufacturer: RENESAS [Renesas Technology Corp]

• Idle cycles between read-read cycles in the same spaces (IWRRS = 01 or more)
• External wait mask specification (WM = 0).
In addition to the above conditions, the following conditions are included depending on the
detection method of DREQ.
• For DREQ level detection: only write access
• For DREQ edge detection: both write access and read access
Phenomenon: The detection timings of the DREQ pin in the above access are shown in figures
13.19 to 13.22.
Bus cycle
DREQ
(Rising edge)
DACK
(High-active)
CKIO
Figure 13.19 Example of DREQ Input Detection in Cycle Steal Mode Edge Detection
Figure 13.20 Example of DREQ Input Detection in Cycle Steal Mode Edge Detection
Bus cycle
DREQ
(Rising edge)
DACK
(High-active)
CKIO
1st acceptance
Non-sensitive period
CPU
1st acceptance
Non-sensitive period
CPU
When DACK is Divided to 4 by Idle Cycles
When DACK is Divided to 2 by Idle Cycles
Non-sensitive period
2nd acceptance
DMAC write or read
Non-sensitive period
2nd acceptance
Section 13 Direct Memory Access Controller (DMAC)
DMAC write or read
Rev. 4.00 Sep. 14, 2005 Page 447 of 982
3rd acceptance is after the
next DACK assertion
3rd acceptance possible
REJ09B0023-0400