HD6417641 RENESAS [Renesas Technology Corp], HD6417641 Datasheet - Page 677

• Manufacturer Part Number: HD6417641
• Manufacturer: RENESAS [Renesas Technology Corp]

18.7
18.7.1
MTU operation can be disabled or enabled using the module standby register.
18.7.2
The input clock pulse width must be at least 1.5 states in the case of single-edge detection, and at
least 2.5 states in the case of both-edge detection. The TPU will not operate properly at narrower
pulse widths.
In phase counting mode, the phase difference and overlap between the two input clocks must be at
least 1.5 states, and the pulse width must be at least 2.5 states. Figure 18.70 shows the input clock
conditions in phase counting mode.
TCLKA
(TCLKC)
TCLKB
(TCLKD)
Notes:
Figure 18.70 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode
Phase difference and overlap
Pulse width
Usage Notes
Module Standby Mode Setting
Input Clock Restrictions
Overlap
Pulse width
Phase
differ-
ence
: 1.5 states or more
: 2.5 states or more
Overlap
Phase
differ-
ence
Pulse width
Section 18 Multi-Function Timer Pulse Unit (MTU)
Pulse width
Rev. 4.00 Sep. 14, 2005 Page 627 of 982
Pulse width
REJ09B0023-0400