HD6417641 RENESAS [Renesas Technology Corp], HD6417641 Datasheet - Page 304

• Manufacturer Part Number: HD6417641
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 11 User Break Controller (UBC)
11.2.10 Execution Times Break Register (BETR)
BETR is a 16-bit readable/writable register. When the execution-times break condition of channel
B is enabled, this register specifies the number of execution times to make the break. The
maximum number is 2
break is issued when the break condition is satisfied after BETR becomes H'0001.
11.2.11 Branch Source Register (BRSR)
BRSR is a 32-bit read-only register. BRSR stores bits 27 to 0 in the address of the branch source
instruction. BRSR has the flag bit that is set to 1 when a branch occurs. This flag bit is cleared to 0
when BRSR is read, the setting to enable PC trace is made, or BRSR is initialized by a power-on
reset. Other bits are not initialized by a power-on reset. The eight BRSR registers have a queue
structure and a stored register is shifted at every branch.
Rev. 4.00 Sep. 14, 2005 Page 254 of 982
REJ09B0023-0400
Bit
15 to 12
11 to 0
Bit
31
30 to 28
27 to 0
Bit Name
SVF

BSA27 to
BSA0
Bit Name

BET11 to
BET0
12
Initial
Value
0
All 0

– 1 times. When a break condition is satisfied, it decreases BETR. A
Initial
Value
All 0
All 0
R/W
R
R/W
R/W
R
R
R
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Number of Execution Times
Description
BRSR Valid Flag
Indicates whether the branch source address is stored.
When a branch source address is fetched, this flag is
set to 1. This flag is cleared to 0 by reading from
BRSR.
0: The value of BRSR register is invalid
1: The value of BRSR register is valid
Reserved
These bits are always read as 0. The write value
should always be 0.
Branch Source Address
Store bits 27 to 0 of the branch source address.