HD6417641 RENESAS [Renesas Technology Corp], HD6417641 Datasheet - Page 474

• Manufacturer Part Number: HD6417641
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 13 Direct Memory Access Controller (DMAC)
13.4
When there is a DMA transfer request, the DMAC starts the transfer according to the
predetermined channel priority order; when the transfer end conditions are satisfied, it ends the
transfer. Transfers can be requested in three modes: auto request, external request, and on-chip
module request. The dual address mode has direct address transfer mode and indirect address
transfer mode. In the bus mode, the burst mode or the cycle steal mode can be selected.
13.4.1
After the DMA source address registers (SAR), DMA destination address registers (DAR), DMA
transfer count registers (DMATCR), DMA channel control registers (CHCR), DMA operation
register (DMAOR), and DMA extension resource selector (DMARS) are set, the DMAC transfers
data according to the following procedure:
1. Checks to see if transfer is enabled (DE = 1, DME = 1, TE = 0, AE = 0, NMIF = 0)
2. When a transfer request comes and transfer is enabled, the DMAC transfers 1 transfer unit of
3. When the specified number of transfer have been completed (when DMATCR reaches 0), the
4. When a NMI interrupt is generated, the transfer is aborted. Transfers are also aborted when the
Rev. 4.00 Sep. 14, 2005 Page 424 of 982
REJ09B0023-0400
data (depending on the TS0 and TS1 settings). For an auto request, the transfer begins
automatically when the DE bit and DME bit are set to 1. The DMATCR value will be
decrement for each transfer. The actual transfer flows vary by address mode and bus mode.
transfer ends normally. If the IE bit of the CHCR is set to 1 at this time, a DEI interrupt is sent
to the CPU.
DE bit of the CHCR or the DME bit of the DMAOR are changed to 0.
Operation
DMA Transfer Flow