HD6417641 RENESAS [Renesas Technology Corp], HD6417641 Datasheet - Page 323

• Manufacturer Part Number: HD6417641
• Manufacturer: RENESAS [Renesas Technology Corp]

12.3
12.3.1
In the architecture of this LSI, both logical spaces and physical spaces have 32-bit address spaces.
The cache access method is shown by the upper three bits. For details see section 7, Cache. The
remaining 29 bits are used for division of the space into ten areas (address map 1) or eight areas
(address map 2) according to the MAP bit in the CMNCR register setting. The BSC performs
control for this 29-bit space.
As listed in tables 12.2 and 12.3, this LSI can connect various memories to eight areas or six areas,
and it outputs chip select signals (CS0, CS2 to CS4, CS5A, CS5B, CS6A, and CS6B) for each of
them. CS0 is asserted during area 0 access; CS5A is asserted during area 5A access when address
map 1 is selected; and CS5B is asserted when address map 2 is selected. Also CS6A is asserted
during area 6A access when address map 1 is selected; and CS6B is asserted when address map 2
is selected.
Name
WE0
RASU
RASL
CASU
CASL
CKE
FRAME
WAIT
BREQ
BACK
MD3
Area Overview
Area Division
Output
Output
Output
Output
Output
Input
Input
Output
Input
I/O
Function
Indicates that D7 to D0 are being written to.
Connected to the byte select signal when a byte-selection SRAM is
connected.
Functions as the selection signals for D7 to D0 when SDRAM is
connected.
Connects to RAS pin when SDRAM is connected.
Connects to CAS pin when SDRAM is connected.
Clock enable for SDRAM
Functions as FRAME signal when connected to burst MPX-IO
interface
External wait input
Bus request input
Bus enable input
MD3: Select area 0 bus width (16/32 bits)
Rev. 4.00 Sep. 14, 2005 Page 273 of 982
Section 12 Bus State Controller (BSC)
REJ09B0023-0400