HD6417641 RENESAS [Renesas Technology Corp], HD6417641 Datasheet - Page 371

• Manufacturer Part Number: HD6417641
• Manufacturer: RENESAS [Renesas Technology Corp]

12.5
12.5.1
This LSI supports big endian, in which the 0 address is the most significant byte (MSByte) in the
byte data.
Three data bus widths (8 bits, 16 bits, and 32 bits) are available for normal memory and byte-
selection SRAM. Two data bus width (16 bits and 32 bits) are available for SDRAM. Data bus
width for MPX-IO is fixed to 32 bits. Data alignment is performed in accordance with the data bus
width of the device. This also means that when longword data is read from a byte-width device,
the read operation must be done four times. In this LSI, data alignment and conversion of data
length is performed automatically between the respective interfaces.
Table 12.5 through 12.7 show the relationship between device data width and access unit.
Table 12.5 32-Bit External Device Access and Data Alignment
Operation
Byte access
at 0
Byte access
at 1
Byte access
at 2
Byte access
at 3
Word access
at 0
Word access
at 2
Longword
access at 0
Operating Description
Endian/Access Size and Data Alignment
D31 to
D24
31 to 24
15 to 8
7 to 0
Data
Data
Data




D23 to
D16
23 to 16
7 to 0
7 to 0
Data
Data
Data




Data Bus
D15 to
D8
15 to 8
15 to 8
7 to 0
Data
Data
Data




D7 to D0
7 to 0
7 to 0
7 to 0
Data
Data
Data




WE3,
DQMUU
Assert
Assert
Assert




Rev. 4.00 Sep. 14, 2005 Page 321 of 982
Section 12 Bus State Controller (BSC)
WE2,
DQMUL
Assert
Assert
Assert
Strobe Signals




WE1,
DQMLU
Assert
Assert
Assert




REJ09B0023-0400
WE0,
DQMLL
Assert
Assert
Assert



