HD6417641 RENESAS [Renesas Technology Corp], HD6417641 Datasheet - Page 198

• Manufacturer Part Number: HD6417641
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 4 Clock Pulse Generator (CPG)
Notes:
Caution: 1. The frequency of the internal clock is the frequency of the signal input to the CKIO
Rev. 4.00 Sep. 14, 2005 Page 148 of 982
REJ09B0023-0400
Clock
operating
mode
6
7
FRQCR
register
setting
H'1303
H'1313
H'1333
H'1000
H'1001
H'1002
H'1003
H'1101
H'1103
H'1111
H'1113
H'1202
H'1222
H'1303
H'1313
H'1333
1. The ratio of clock frequencies, where the input clock frequency is assumed to be 1.
2. In modes 2 and 6, the frequency of the clock input from the EXTAL pin or the
2. The frequency of the peripheral clock is the frequency of the signal input to the CKIO
3. The frequency multiplier of the PLL circuit can be selected as x1, x2, x3 or x4. The
4. The signal output by PLL circuit 1 is the signal on the CKIO pin multiplied by the
PLL
Circuit 1
ON (×4)
ON (×4)
ON (×4)
ON (×1)
ON (×1)
ON (×1)
ON (×1)
ON (×2)
ON (×2)
ON (×2)
ON (×2)
ON (×3)
ON (×3)
ON (×4)
ON (×4)
ON (×4)
frequency of the crystal resonator. In mode 7, the frequency of the clock input from
the CKIO pin.
pin after multiplication by the frequency-multiplier of PLL circuit 1 and division by the
divider's divisor. Do not set a frequency for the internal clock below the frequency of
the signal on the CKIO pin.
pin after multiplication by the frequency-multiplier of PLL circuit 1 and division by the
divider's divisor. Set the frequency of the peripheral clock to 33.33 MHz or below. In
addition, do not set a higher frequency for the internal clock than the frequency on
the CKIO pin.
divisor of the divider can be selected as x1, x1/2, x1/3 or x1/4. The settings are made
in the respective frequency-control registers.
frequency multiplier of PLL circuit 1. Ensure that the frequency of the signal from PLL
circuit 1 is no more than 100 MHz.
PLL frequency
multiplier
PLL
Circuit 2
ON (×2)
ON (×2)
ON (×2)
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
Ratio of internal
clock frequencies
(I:B:P)
8:2:2
4:2:2
2:2:2
1:1:1
1:1:1/2
1:1:1/3
1:1:1/4
2:1:1
2:1:1/2
1:1:1
1:1:1/2
3:1:1
1:1:1
4:1:1
2:1:1
1:1:1
10 to 12.5
Input clock
10 to 16.66
10 to 16.66
20 to 33.33
20 to 50
20 to 50
20 to 50
20 to 33.33
20 to 50
20 to 33.33
20 to 50
26.66 to 33.33 26.66 to 33.33 80 to 100
26.66 to 33.33 26.66 to 33.33 26.66 to 33.33 26.66 to 33.33 26.66 to 33.33
20 to 25
20 to 33.33
20 to 33.33
Output clock
(CKIO pin)
20 to 25
20 to 33.33
20 to 33.33
20 to 33.33
20 to 50
20 to 50
20 to 50
20 to 33.33
20 to 50
20 to 33.33
20 to 50
20 to 25
20 to 33.33
20 to 33.33
Selectable frequency ranges (MHz)
Internal clock Bus clock
80 to 100
40 to 66.66
20 to 33.33
20 to 33.33
20 to 50
20 to 50
20 to 50
40 to 66.66
40 to 100
20 to 33.33
20 to 50
80 to 100
40 to 66.66
20 to 33.33
20 to 25
20 to 33.33
20 to 33.33
20 to 33.33
20 to 50
20 to 50
20 to 50
20 to 33.33
20 to 50
20 to 33.33
20 to 50
26.66 to 33.33 26.66 to 33.33
20 to 25
20 to 33.33
20 to 33.33
Peripheral clock
20 to 25
20 to 33.33
20 to 33.33
20 to 33.33
10 to 25
6.66 to 16.66
5 to 12.5
20 to 33.33
10 to 25
20 to 33.33
10 to 25
20 to 25
20 to 33.33
20 to 33.33