HD6417641 RENESAS [Renesas Technology Corp], HD6417641 Datasheet - Page 993

• Manufacturer Part Number: HD6417641
• Manufacturer: RENESAS [Renesas Technology Corp]

(Bank Active Mode: ACT + READ Commands, CAS Latency 2, WTRCD = 0 Cycle)
Figure 25.31 Synchronous DRAM Burst Read Bus Cycle (Four Read Cycles)
A12/A11*
D31 to D0
A25 to A0
DACKn*
RASU/L
CASU/L
RD/WR
DQMxx
CKIO
CKE
CSn
BS
1
2
Note:
t
t
t
t
t
t
t
AD1
RASD1
DQMD1
AD1
RWD1
CSD1
DACD
1. An address pin to be connected to pin A10 of SDRAM.
2. Waveform for DACKn when active low is selected.
address
Tr
Row
t
t
t
t
AD1
AD1
t
CASD1
RASD1
BSD
Tc1
t
AD1
Tc2
address
Column
t
AD1
Td1
Tc3
t
(High)
RDS2
Read command
t
AD1
t
RDH2
Td2
Tc4
Rev. 4.00 Sep. 14, 2005 Page 943 of 982
t
t
BSD
CASD1
Td3
Section 25 Electrical Characteristics
Td4
t
RDS2
t
t
t
t
DQMD1
CSD1
RDH2
DACD
Tde
REJ09B0023-0400
t
t
t
AD1
RWD1
AD1