HD6417641 RENESAS [Renesas Technology Corp], HD6417641 Datasheet - Page 125

• Manufacturer Part Number: HD6417641
• Manufacturer: RENESAS [Renesas Technology Corp]

Notes: 1. The normal minimum number of execution cycles is two, but five cycles are required
Logic Operation Instructions
Table 2.21 Logic Operation Instructions
Instruction
SUBV
Instruction
AND
AND
AND.B
NOT
OR
OR
OR.B
TAS.B
TST
TST
TST.B
XOR
XOR
XOR.B
2. The normal minimum number of execution cycles is one, but three cycles are required
Rm,Rn
Rm,Rn
#imm,R0
#imm,@(R0,GBR)
Rm,Rn
Rm,Rn
#imm,R0
#imm,@(R0,GBR)
@Rn
Rm,Rn
#imm,R0
#imm,@(R0,GBR)
Rm,Rn
#imm,R0
#imm,@(R0,GBR)
when the operation result is read from the MAC register immediately after the
instruction.
when the operation result is read from the MAC register immediately after the MUL
instruction.
Instruction Code
0011nnnnmmmm1011
Instruction Code
0010nnnnmmmm1001
11001001iiiiiiii
11001101iiiiiiii
0110nnnnmmmm0111
0010nnnnmmmm1011
11001011iiiiiiii
11001111iiiiiiii
0100nnnn00011011
0010nnnnmmmm1000
11001000iiiiiiii
11001100iiiiiiii
0010nnnnmmmm1010
11001010iiiiiiii
11001110iiiiiiii
Operation
Rn–Rm → Rn, Underflow → T 1
Operation
Rn & Rm → Rn
R0 & imm → R0
(R0 + GBR) & imm →
(R0 + GBR)
~Rm → Rn
Rn | Rm → Rn
R0 | imm → R0
(R0 + GBR) | imm →
(R0 + GBR)
If (Rn) is 0, 1 → T;
1 → MSB of (Rn)
Rn & Rm; if the result
is 0, 1 → T
R0 & imm; if the result
is 0, 1 → T
(R0 + GBR) & imm;
if the result is 0, 1 → T
Rn ^ Rm → Rn
R0 ^ imm → R0
(R0 + GBR) ^ imm →
(R0 + GBR)
Rev. 4.00 Sep. 14, 2005 Page 75 of 982
Execution
States
Execution
States
1
1
3
1
1
1
3
4
1
1
3
1
1
3
REJ09B0023-0400
Section 2 CPU
T Bit
Underflow
T Bit
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Test
result
Test
result
Test
result
Test
result
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