HD6417641 RENESAS [Renesas Technology Corp], HD6417641 Datasheet - Page 101

• Manufacturer Part Number: HD6417641
• Manufacturer: RENESAS [Renesas Technology Corp]

2.4.2
Two different memory accesses are made with DSP instructions. The two kinds of instructions are
X and Y data transfer instructions (MOVX.W and MOVY.W) and single data transfer instructions
(MOVS.W and MOVSL). The data addressing is different for these two kinds of instructions. An
overview of the data transfer instructions is given in table 2.12.
Table 2.12 Overview of Data Transfer Instructions
Addressing
Mode
Immediate
Address register
Index register
Addressing
Modulo addressing
Data bus
Data length
Bus contention
Memory
Source register
Destination register
DSP Data Addressing
Instruction
Format
#imm:8
#imm:8
#imm:8
X/Y Data Transfer Processing
(MOVX.W, MOVY.W)
Ax: R4, R5, Ay: R6, R7
Ix: R8, Iy: R9
Nop/Inc (+2)/index addition:
post-increment

Possible
XDB, YDB
16 bits (word)
No
X/Y data memory
Dx, Dy: A0, A1
Dx: X0/X1, Dy: Y0/Y1
Effective Address Calculation Method
8-bit immediate data imm of TST, AND, OR,
or XOR instruction is zero-extended.
8-bit immediate data imm of MOV, ADD, or
CMP/EQ instruction is sign-extended.
8-bit immediate data imm of TRAPA
instruction
is zero-extended and multiplied by 4.
As: R2, R3, R4, R5
Not possible
16/32 bits (word/longword)
Yes
Single Data Transfer Processing
(MOVS.W, MOVS.L)
Is: R8
Nop/Inc (+2, +4)/index addition:
post-increment
Dec (–2, –4): pre-decrement
LDB
Entire memory space
Ds: A0/A1, M0/M1, X0/X1, Y0/Y1, A0G, A1G
Ds: A0/A1, M0/M1, X0/X1, Y0/Y1, A0G, A1G
Rev. 4.00 Sep. 14, 2005 Page 51 of 982
Calculation Formula
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REJ09B0023-0400
Section 2 CPU