HD6417641 RENESAS [Renesas Technology Corp], HD6417641 Datasheet - Page 379

• Manufacturer Part Number: HD6417641
• Manufacturer: RENESAS [Renesas Technology Corp]

12.5.3
Wait cycle insertion on a normal space access can be controlled by the settings of bits WR3 to
WR0 in CSnWCR. It is possible for areas 4, 5A, and 5B to insert wait cycles independently in
read access and in write access. The areas other than 4, 5A, and 5B have common access wait for
read cycle and write cycle. The specified number of Tw cycles are inserted as wait cycles in a
normal space access shown in figure 12.9.
Access Wait Control
Figure 12.9 Wait Timing for Normal Space Access (Software Wait Only)
Read
Write
Note: * The waveform for DACKn is when active low is specified.
D31 to D0
D31 to D0
A25 to A0
DACKn*
RD/WR
CKIO
WEn
CSn
RD
BS
T1
Tw
Rev. 4.00 Sep. 14, 2005 Page 329 of 982
Section 12 Bus State Controller (BSC)
T2
REJ09B0023-0400