HD6417641 RENESAS [Renesas Technology Corp], HD6417641 Datasheet - Page 985

• Manufacturer Part Number: HD6417641
• Manufacturer: RENESAS [Renesas Technology Corp]

25.3.7
Synchronous DRAM Timing
(Auto Precharge, CAS Latency 2, WTRCD = 0 Cycle, WTRP = 0 Cycle)
A12/A11*
D31 to D0
A25 to A0
DACKn*
RASU/L
CASU/L
RD/WR
DQMxx
CKIO
CKE
CSn
Figure 25.23 Synchronous DRAM Single Read Bus Cycle
BS
1
2
Note: 1. An address pin to be connected to pin A10 of SDRAM.
2. Waveform for DACKn when active low is selected.
t
t
t
t
t
t
RASD1
t
AD1
CSD1
RWD1
DQMD1
AD1
DACD
Tr
address
Row
t
t
t
t
t
AD1
BSD
RASD1
CASD1
AD1
Tc1
Column address
command
ReadA
t
t
t
BSD
AD1
CASD1
Tcw
(High)
Td1
t
RDS2
Rev. 4.00 Sep. 14, 2005 Page 935 of 982
t
t
CSD1
t
t
DQMD1
DACD
RDH2
Section 25 Electrical Characteristics
Tde
t
t
AD1
RWD1
REJ09B0023-0400