HD6417641 RENESAS [Renesas Technology Corp], HD6417641 Datasheet - Page 356

• Manufacturer Part Number: HD6417641
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 12 Bus State Controller (BSC)
SDRAM*:
• CS2WCR
Rev. 4.00 Sep. 14, 2005 Page 306 of 982
REJ09B0023-0400
Bit
1
0
Bit
31 to 11
10
9
8
7
6 to 0
Bit Name
HW1
HW0
Bit Name



A2CL1
A2CL0

Initial
Value
0
0
Initial
Value
All 0
1
0
1
0
All 0
R/W
R/W
R/W
R/W
R
R
R
R/W
R/W
R
Description
Delay Cycles from RD, WEn Negation to Address, CSn
Negation
Specify the number of delay cycles from RD and WEn
negation to address and CSn negation.
00: 0.5 cycles
01: 1.5 cycles
10: 2.5 cycles
11: 3.5 cycles
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Reserved
This bit is always read as 1. The write value should
always be 1.
Reserved
This bit is always read as 0. The write value should
always be 0.
CAS Latency for Area 2
Specify the CAS latency for area 2.
00: 1 cycle
01: 2 cycles
10: 3 cycles
11: 4 cycles
Reserved
These bits are always read as 0. The write value
should always be 0.