HD6417641 RENESAS [Renesas Technology Corp], HD6417641 Datasheet - Page 443

• Manufacturer Part Number: HD6417641
• Manufacturer: RENESAS [Renesas Technology Corp]

Table 12.21 Minimum Number of Idle Cycles between Access Cycles of CPU and the DMAC
CSnBCR
Idle
Setting
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
BSC Register Setting
CS3WCR.
WTRP
Setting
0
0
0
0
1
1
1
1
2
2
2
2
3
3
3
3
0
0
0
0
1
1
1
1
2
2
2
Dual Address Mode for the SDRAM Interface
CS3WCR.
TRWL
Setting
0
1
2
3
0
1
2
3
0
1
2
3
0
1
2
3
0
1
2
3
0
1
2
3
0
1
2
Read to
Read
1/1/1/2
1/1/1/2
1/1/1/2
1/1/1/2
2/2/2/2
2/2/2/2
2/2/2/2
2/2/2/2
3/3/3/3
3/3/3/3
3/3/3/3
3/3/3/3
4/4/4/4
4/4/4/4
4/4/4/4
4/4/4/4
2/2/2/2
2/2/2/2
2/2/2/2
2/2/2/2
2/2/2/2
2/2/2/2
2/2/2/2
2/2/2/2
3/3/3/3
3/3/3/3
3/3/3/3
Write to
Write
1/1/2/3
1/1/2/3
2/2/2/3
3/3/3/3
1/1/2/3
2/2/2/3
3/3/3/3
4/4/4/4
2/2/2/3
3/3/3/3
4/4/4/4
5/5/5/5
3/3/3/3
4/4/4/4
5/5/5/5
6/6/6/6
1/1/2/3
1/1/2/3
2/2/2/3
3/3/3/3
1/1/2/3
2/2/2/3
3/3/3/3
4/4/4/4
2/2/2/3
3/3/3/3
4/4/4/4
CPU Access
Read to
Write
3/3/4/5
3/3/4/5
3/3/4/5
3/3/4/5
3/3/4/5
3/3/4/5
3/3/4/5
3/3/4/5
3/3/4/5
3/3/4/5
3/3/4/5
3/3/4/5
4/4/4/5
4/4/4/5
4/4/4/5
4/4/4/5
3/3/4/5
3/3/4/5
3/3/4/5
3/3/4/5
3/3/4/5
3/3/4/5
3/3/4/5
3/3/4/5
3/3/4/5
3/3/4/5
3/3/4/5
Rev. 4.00 Sep. 14, 2005 Page 393 of 982
Section 12 Bus State Controller (BSC)
Write to
Read
0/0/0/0
1/1/1/1
2/2/2/2
3/3/3/3
1/1/1/1
2/2/2/2
3/3/3/3
4/4/4/4
2/2/2/2
3/3/3/3
4/4/4/4
5/5/5/5
3/3/3/3
4/4/4/4
5/5/5/5
6/6/6/6
1/1/1/1
1/1/1/1
2/2/2/2
3/3/3/3
1/1/1/1
2/2/2/2
3/3/3/3
4/4/4/4
2/2/2/2
3/3/3/3
4/4/4/4
Read to
Write
2
2
2
2
2
2
2
2
3
3
3
3
4
4
4
4
2
2
2
2
2
2
2
2
3
3
3
DMAC Access
REJ09B0023-0400
Write to
Read
0
1
2
3
1
2
3
4
2
3
4
5
3
4
5
6
1
1
2
3
1
2
3
4
2
3
4