HD6417641 RENESAS [Renesas Technology Corp], HD6417641 Datasheet - Page 479

• Manufacturer Part Number: HD6417641
• Manufacturer: RENESAS [Renesas Technology Corp]

13.4.3
When the DMAC receives simultaneous transfer requests on two or more channels, it selects a
channel according to a predetermined priority order. The four modes (fixed mode 1, fixed mode 2,
channel selective round-robin mode, and all-channel round-robin mode) are selected using the
priority bits PR0, PR1, and RC0 to RC3 in the DMA operation register (DMAOR).
Fixed Mode: In these modes, the priority levels among the channels remain fixed. There are two
kinds of fixed modes as follows:
CHCR
RS[3:0] MID
1000
Channel Priority
101010 00
110000 00
110010 00
110100 00
111010 00
101000 00
101100 00
111100 00
Fixed mode 1: CH0 > CH1 > CH2 > CH3
Fixed mode 2: CH0 > CH2 > CH3 > CH1
DMARS
RID
01
DMA
Transfer
Request
Source
MTU0
MTU1
MTU2
MTU3
MTU4
USB transmitter EP2FIFO empty transfer
USB
receiver
A/D converter 1 ADI (A/D conversion
CMT1
DMA Transfer
Request Signal
TGI0A
(input capture interrupt/
compare match interrupt)
TGI1A
(input capture interrupt/
compare match interrupt)
TGI2A
(input capture interrupt/
compare match interrupt)
TGI3A
(input capture interrupt/
compare match interrupt)
TGI4A
(input capture interrupt/
compare match interrupt)
request
EP1FIFO full transfer
request
end interrupt)
Compare-match transfer
request
Section 13 Direct Memory Access Controller (DMAC)
Rev. 4.00 Sep. 14, 2005 Page 429 of 982
Source
Any
Any
Any
Any
Any
Any
USBEPDR1 Any
ADDR1
Any
Desti-
nation
Any
Any
Any
Any
Any
USBEPDR2 Cycle steal
Any
Any
REJ09B0023-0400
Bus Mode
Burst/
cycle steal
Burst/
cycle steal
Burst/
cycle steal
Burst/
cycle steal
Burst/
cycle steal
Cycle steal
Cycle steal
Burst/
cycle steal