HD6417641 RENESAS [Renesas Technology Corp], HD6417641 Datasheet - Page 41

• Manufacturer Part Number: HD6417641
• Manufacturer: RENESAS [Renesas Technology Corp]

Figure 25.27 Synchronous DRAM Single Write Bus Cycle
Figure 25.28 Synchronous DRAM Single Write Bus Cycle (Auto Precharge,
Figure 25.29 Synchronous DRAM Burst Write Bus Cycle (Four Write Cycles)
Figure 25.30 Synchronous DRAM Burst Write Bus Cycle (Four Write Cycles)
Figure 25.31 Synchronous DRAM Burst Read Bus Cycle (Four Read Cycles) (Bank Active
Figure 25.32 Synchronous DRAM Burst Read Bus Cycle (Four Read Cycles)
Figure 25.33 Synchronous DRAM Burst Read Bus Cycle (Four Read Cycles)
Figure 25.34 Synchronous DRAM Burst Write Bus Cycle (Four Write Cycles)
Figure 25.35 Synchronous DRAM Burst Write Bus Cycle (Four Write Cycles)
Figure 25.36 Synchronous DRAM Burst Write Bus Cycle (Four Write Cycles)
Figure 25.37 Synchronous DRAM Auto-Refreshing Timing (WTRP = 1 Cycle,
Figure 25.38 Synchronous DRAM Self-Refreshing Timing (WTRP = 1 Cycle) ...................... 950
Figure 25.39 Synchronous DRAM Mode Register Write Timing (WTRP = 1 Cycle)............... 951
Figure 25.40 Synchronous DRAM Access Timing in Low-Frequency Mode
Figure 25.41 Synchronous DRAM Self-Refreshing Timing in Low-Frequency Mode
Figure 25.42 SCK Input Clock Timing....................................................................................... 954
Figure 25.43 SCIF Input/Output Timing in Synchronous Mode ................................................ 955
Figure 25.44 I/O Port Timing ..................................................................................................... 955
Figure 25.45 DREQ Input Timing.............................................................................................. 955
Figure 25.46 DACK, TEND Output Timing .............................................................................. 955
Figure 25.47 MTU Input/Output Timing.................................................................................... 956
(Auto Precharge, TRWL = 1 Cycle) ..................................................................... 939
WTRCD = 2 Cycles, TRWL = 1 Cycle) ............................................................... 940
(Auto Precharge, WTRCD = 0 Cycle, TRWL = 1 Cycle) .................................... 941
(Auto Precharge, WTRCD = 1 Cycle, TRWL = 1 Cycle) .................................... 942
Mode: ACT + READ Commands, CAS Latency 2, WTRCD = 0 Cycle) ............ 943
(Bank Active Mode: READ Command, Same Row Address, CAS Latency 2,
WTRCD = 0 Cycle)
(Bank Active Mode: PRE + ACT + READ Commands, Different
Row Addresses, CAS Latency 2, WTRCD = 0 Cycle) ........................................ 945
(Bank Active Mode: ACT + WRITE Commands, WTRCD = 0 Cycle,
TRWL = 0 Cycle) ................................................................................................. 946
(Bank Active Mode: WRITE Command, Same Row Address,
WTRCD = 0 Cycle, TRWL = 0 Cycle)................................................................. 947
(Bank Active Mode: PRE + ACT + WRITE Commands,
Different Row Addresses, WTRCD = 0 Cycle, TRWL = 0 Cycle) ..................... 948
WTRC = 3 Cycles)................................................................................................ 949
(Auto-Precharge, TRWL = 2 Cycles) ................................................................... 952
(WTRP = 2 Cycles)............................................................................................... 953
................................................................................................ 944
Rev. 4.00 Sep. 14, 2005 Page xli of l