HD6417641 RENESAS [Renesas Technology Corp], HD6417641 Datasheet - Page 354

• Manufacturer Part Number: HD6417641
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 12 Bus State Controller (BSC)
Rev. 4.00 Sep. 14, 2005 Page 304 of 982
REJ09B0023-0400
Bit
17
16
15 to 13
12
11
Bit Name
BW1
BW0

SW1
SW0
Initial
Value
0
0
All 0
0
0
R/W
R/W
R/W
R
R/W
R/W
Description
Number of Burst Wait Cycles
Specify the number of wait cycles to be inserted
between the second or later access cycles in burst
access.
00: No cycle
01: 1 cycle
10: 2 cycles
11: 3 cycles
Reserved
These bits are always read as 0. The write value
should always be 0.
Number of Delay Cycles from Address, CSn Assertion
to RD, WE Assertion
Specify the number of delay cycles from address and
CSn assertion to RD and WE assertion.
00: 0.5 cycles
01: 1.5 cycles
10: 2.5 cycles
11: 3.5 cycles