M3087BFLBGP#U5 Renesas Electronics America, M3087BFLBGP#U5 Datasheet - Page 102

• Manufacturer Part Number: M3087BFLBGP#U5
• Description: IC M32C/87 MCU FLASH 144LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M3087BFLBGP#U5

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IEBus, IrDA, SIO, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 121
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 34x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 144-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
REJ09B0180-0151 Rev.1.51 Jul 31, 2008
Page 78 of 587
Figure 8.11
8.2.7
Table 8.8
NOTE:
Clock generation circuits
CPU
Internal peripheral circuits
RD, WR, A0 to A22, A23, D0 to D15, CS0 to CS3, BHE
HLDA
ALE
Programmable I/O ports
1. When the PM22 bit in the PM2 register is set to 1 (selects the on-chip oscillator clock as count source for the
- Separate bus (bus cycle is 1
The HOLD input signal is used to transfer ownership of the bus from the CPU to external devices. When a low-
level (“L”) signal is applied to the HOLD pin, the MCU enters a hold state after the bus access in progress is
completed. While the HOLD pin is held “L”, the MCU remains in a hold state and the HLDA pin outputs an
“L” signal. Table 8.8 lists the MCU states in hold state.
Bus is used in the following priority order: HOLD, DMAC, CPU.
watchdog timer), watchdog timer does not stop.
BCLK
CSi
RD
RDY
i = 0 to 3
tsu(RDY-BCLK): RDY input setup time
NOTE:
1. Chip-select output (CSi) may be extended depending on the CPU state such as the instruction queue buffer.
(1)
HOLD Input
: Wait states inserted by RDY input
RD Output Signal Extended by RDY Input
MCU States in Hold State
tsu(RDY-BCLK)
Timing to input RDY signal
Item
φ
+ 2
φ
)
- Multiplexed bus (bus cycle is 2
Operating (oscillating)
Stopped
Operating
(Watchdog timer is stopped)
High-impedance
Outputs “L”
Outputs “L”
Maintains the same state as when “L” is input to HOLD pin.
BCLK
CSi
RD
RDY
(1)
tsu(RDY-BCLK)
State
Timing to input RDY signal
(1)
φ
+ 2
φ
)
8. Bus