M3087BFLBGP#U5 Renesas Electronics America, M3087BFLBGP#U5 Datasheet - Page 414

• Manufacturer Part Number: M3087BFLBGP#U5
• Description: IC M32C/87 MCU FLASH 144LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M3087BFLBGP#U5

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IEBus, IrDA, SIO, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 121
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 34x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 144-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M32C/87 Group (M32C/87, M32C/87A, M32C/87B) 22. Intelligent I/O (Group 0 and 1 Communication Function)
REJ09B0180-0151 Rev.1.51 Jul 31, 2008
Page 390 of 587
Table 22.21
Table 22.22
NOTES:
Table 22.23
m: Setting value of the G1PO0 register (0001h to FFFDh)
NOTES:
Interrupt request
generation timing
f1
f8
f2n
f1
f8
f2n
1. The transfer clock is generated when the RSHTE bit in the G0ERC register is set to 1 (receive shift operation
2. Bits CNT3 to CNT0 in the TCSPR register select no division (n = 0) or divide-by-2n (n = 1 to 15).
1. The transfer clock is generated when the RSHTE bit in the G1ERC register is set to 1(receive shift operation
2. The transfer clock is generated in single-phase waveform output mode of the channel 1.
3. Bits CNT3 to CNT0 in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15).
(2)
(3)
fBT1
m+2
enabled) while source data is generated.
enabled) while source data is generated.
Transfer Clock
Transfer Clock
Item
Specifications of the HDLC Data Processing Mode (2/2)
Clock Settings in HDLC Data Processing Mode (Group 0)
Clock Setting in HDLC Data Processing Mode (Group 1)
(NOTE 2)
(1)
(1)
When HDLC frame data is generated:
When source data is generated:
• The IRS bit in the GiMR register selects one of the following:
• When data, which is already converted to HDLC frame data, is transferred from the
• When data is transferred from the GiRI register to the GiRB register (receive
• When receive data is transferred from the receive buffer in the GiRI register to the
• When the GiTB register is compared to the GiCMPj register (j = 0 to 3), the SRTiR bit
- When the IRS bit is set to 0 (no data in the GiTB register)
- When the IRS bit is set to 1 (transmit operation completed)
When one of the above occurs, the GiTOR bit in the IIO1IR or IIO3IR register
becomes 1 (interrupt requested) (Refer to Figure 11.18).
transmit shift register of the GiTO register to the transmit buffer, the GiTOR bit
becomes 1.
operation completed), the GiRIR bit in the IIO0IR or IIO2IR register becomes 1
(interrupt requested).
receive shift register, the GiRIR bit becomes 1.
in the IIO4IR register becomes 1 (interrupt requested).
When data is transferred from the GiTB register to the transmit shift register
(transmit operation started).
When data transfer from the transmit shift register to the GiTO register is
completed.
CCS0 Bit
CCS2 Bit
1
1
0
0
0
1
1
CCS Register
CCS Register
Specification
CCS1 Bit
CCS3 Bit
0
1
1
0
0
1
1