M3087BFLBGP#U5 Renesas Electronics America, M3087BFLBGP#U5 Datasheet - Page 145

• Manufacturer Part Number: M3087BFLBGP#U5
• Description: IC M32C/87 MCU FLASH 144LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M3087BFLBGP#U5

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IEBus, IrDA, SIO, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 121
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 34x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 144-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
REJ09B0180-0151 Rev.1.51 Jul 31, 2008
Page 121 of 587
Figure 11.10
Peripheral function interrupt priority
(if priority levels are the same)
Low
High
start or stop condition detection
UART0 transmission/NACK
UART1 transmission/NACK
UART2 transmission/NACK
UART3 transmission/NACK
UART4 transmission/NACK
UART0 reception/ACK
UART1 reception/ACK
UART2 reception/ACK
UART3 reception/ACK
UART4 reception/ACK
Interrupt priority level
Bus conflict/
Timer A0
Timer A1
Timer A2
Timer A3
Timer A4
Timer B0
Timer B1
Timer B2
Timer B3
Timer B4
Timer B5
(UART2)
Interrupt Priority Level Decision Circuit
DMA0
DMA1
DMA2
DMA3
INT5
INT4
INT3
INT2
INT1
INT0
Level 0 (initial value)
start or stop condition detection
start or stop condition detection
CAN00/UART6 reception/INT6
CAN01/UART6 transmission/
CAN11/UART5 transmission
Intelligent I/O interrupt 10/
Intelligent I/O interrupt 11/
CAN10/UART5 reception
oscillation stop detection,
Intelligent I/O interrupt 0/
Intelligent I/O interrupt 5/
Intelligent I/O interrupt 9/
Intelligent I/O interrupt 2
Intelligent I/O interrupt 3
Intelligent I/O interrupt 4
Intelligent I/O interrupt 6
Intelligent I/O interrupt 7
Intelligent I/O interrupt 8
Intelligent I/O interrupt 1/
CAN12/CAN1 wake-up
Bits RLVL2 to RLVL0
Interrupt priority level
Key input interrupt
(UART0, UART3)
(UART1, UART4)
Watchdog timer,
Vdet4 detection
Address match
CAN02/INT8
Bus conflict/
Bus conflict/
DMACII
A/D0
INT7
I flag
NMI
IPL
Interrupt priority level
decision output
(to the clock generation
circuit)
Interrupt request
acknowledged
(to CPU)
11. Interrupts