M3087BFLBGP#U5 Renesas Electronics America, M3087BFLBGP#U5 Datasheet - Page 574

• Manufacturer Part Number: M3087BFLBGP#U5
• Description: IC M32C/87 MCU FLASH 144LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M3087BFLBGP#U5

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IEBus, IrDA, SIO, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 121
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 34x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 144-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
REJ09B0180-0151 Rev.1.51 Jul 31, 2008
Page 550 of 587
Switching Characteristics
(VCC1 = VCC2 = 3.0 to 3.6 V, VSS = 0 V, Topr = -20 to 85°C unless otherwise specified)
Table 27.52
NOTES:
td(BCLK-AD)
th(BCLK-AD)
th(RD-AD)
th(WR-AD)
td(BCLK-CS)
th(BCLK-CS)
th(RD-CS)
th(WR-CS)
td(BCLK-RD)
th(BCLK-RD)
td(BCLK-WR)
th(BCLK-WR)
td(DB-WR)
th(WR-DB)
tw(WR)
1. Values, which depend on BCLK frequency, can be obtained from the following equations.
2. Values, which depend on BCLK frequency and external bus cycles, can be obtained from the following
3. tc [ns] is added when recovery cycle is inserted.
Symbol
equations.
td(DB-WR)
tw(WR)
th(WR-DB) =
th(WR-AD) =
th(WR-CS) =
Memory Expansion Mode and Microprocessor Mode (when accessing external
memory space)
Address output delay time
Address output hold time (BCLK standard)
Address output hold time (RD standard)
Address output hold time (WR standard)
Chip-select signal output delay time
Chip-select signal output hold time (BCLK standard)
Chip-select signal output hold time (RD standard)
Chip-select signal output hold time (WR standard)
RD signal output delay time
RD signal output hold time
WR signal output delay time
WR signal output hold time
Data output delay time (WR standard)
Data output hold time (WR standard)
WR output width
=
=
f(BCLK) × 2
f(BCLK) × 2
f(BCLK) × 2
f(BCLK) × 2
10
10
f(BCLK)
9
9
10
10
10
× m
× n
9
9
9
- 20 [ns] (if external bus cycle is a φ + b φ , m = b)
- 15 [ns] (if external bus cycle is a φ + b φ , n = (b × 2) - 1)
- 20 [ns]
- 15 [ns]
- 10 [ns]
Parameter
(3)
(3)
(3)
(3)
(3)
Measurement
See Figure
Condition
27.2
VCC1 = VCC2 = 3.3 V
27. Electrical Characteristics
(note 1)
(note 1)
(note 2)
(note 1)
(note 2)
Min.
-3
-3
-5
0
0
0
Standard
Max.
18
18
18
18
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns