M3087BFLBGP#U5 Renesas Electronics America, M3087BFLBGP#U5 Datasheet - Page 432

• Manufacturer Part Number: M3087BFLBGP#U5
• Description: IC M32C/87 MCU FLASH 144LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M3087BFLBGP#U5

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IEBus, IrDA, SIO, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 121
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 34x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 144-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
REJ09B0180-0151 Rev.1.51 Jul 31, 2008
Page 408 of 587
Figure 23.4
23.1.2
23.1.2.1
23.1.2.2
CANi Control Register 1 (i = 0, 1)
b7
The BANKSEL bit in the C0CTLR1 register selects the registers allocated to addresses 0220h to 023Fh. The
BANKSEL bit in the C1CTLR1 register selects the registers allocated to addresses 02A0h to 02BFh.
Registers CiSSCTLR, CiSSSTR, and CiMCTL0 to CiMCTL15 can be accessed by setting the BANKSEL bit to
0. Registers CiGMR0 to CiGMR4, CiLMAR0 to CiLMAR4, and CiLMBR0 to CiLMBR4 can be accessed by
setting the BANKSEL bit to 1.
The INTSEL bit determines whether three types of interrupts (CANi transmit interrupt, CANi receive interrupt
and CANi error interrupt) are output via OR gate or output individually.
Refer to 23.4 CAN Interrupts for details.
NOTE:
b6 b5 b4
NOTE:
1. Change the INTSEL bit setting when the STATE_RESET bit in the CiSTR register is 1 (CAN module is
0
1.The value is obtained by setting the SLEEP bit in the CiSLPR register to 1 (sleep mode exited) after reset and supplying the clock
to the CAN module.
in reset).
0
CANi Control Register 1 (CiCTLR1 Register) (i = 0, 1)
b3
b2
C0CTLR1 and C1CTLR1 Registers
BANKSEL Bit
INTSEL Bit
0
b1
b0
Bit Symbol
BANKSEL
INTSEL
(b1-b0)
(b5-b4)
(b2)
(b7)
Symbol
C0CTLR1
C1CTLR1
−
−
−
−
Unimplemented.
Write 0. Read as undefined value.
Reserved bit
CANi bank switch bit
Reserved bits
CANi interrupt mode select bit
Unimplemented.
Write 0. Read as undefined value.
Bit Name
Address
0241h
0251h
Set to 0
0: Message slot control register and single-shot
1: Mask register selected
Set to 0
0: Output 3 types of interrupt via OR gate
1: Output 3 types of interrupt individually
register selected
Function
After Reset
X000 00XXb
X000 00XXb
23. CAN Module
(1)
RW
RW
RW
RW
RW
−
−