M3087BFLBGP#U5 Renesas Electronics America, M3087BFLBGP#U5 Datasheet - Page 287

• Manufacturer Part Number: M3087BFLBGP#U5
• Description: IC M32C/87 MCU FLASH 144LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M3087BFLBGP#U5

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IEBus, IrDA, SIO, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 121
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 34x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 144-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
REJ09B0180-0151 Rev.1.51 Jul 31, 2008
Page 263 of 587
17.1.6
Table 17.19
NOTES:
Data format
Baud rate
Transmit/receive control
Transmit start condition
Receive start condition
Interrupt request generation
timing
Error detection
1. Bits CNT3 to CNT0 in the TCSPR register select no division (n = 0) or divide-by-2n (n = 1 to 15).
2. If an overrun error occurs, a read from the UiRB register returns undefined values. The IR bit in the SiRIC
In SIM mode, the MCU can communicate with SIM interface devices using UART mode. Both direct and
inverse formats are available. The TXDi pin (i = 0 to 4) outputs a low-level (“L”) signal when a parity error is
detected.
Table 17.19 lists specifications of SIM mode. Table 17.20 list pin settings. Figure 17.32 lists register settings.
Figure 17.33 shows an example of SIM interface operation. Figure 17.34 shows an example of SIM interface
connection.
register remains unchanged as 0 (interrupt not requested).
Special Mode 4 (SIM Mode)
Item
SIM Mode Specifications
• Data length 8-bit UART mode
• One stop bit
• Direct format:
• Inverse format:
Set the CKDIR bit in the UiMR register is 0 (internal clock):
CTS/RTS function disabled
To start transmit operation, all of the following must be met:
To start receive operation, all of the following must be met:
Transmit interrupt:
Receive interrupt:
• Overrun error
• Framing error
• Parity error
• Error sum flag
Parity: even
Data logic: direct (not inverted)
Bit order: LSB first
Parity: odd
Data logic: inverse (inverted)
Bit order: MSB first
• Set the TE bit in the UiC1 register to 1 (transmit operation enabled)
• The TI bit in the UiC1 register is 0 (data in the UiTB register)
• Set the RE bit in the UiC1 register to 1 (receive operation enabled)
• The start bit is detected
• Set the UiIRS bit in the UiC1 register to 1 (transmit operation completed)
• when data is transferred from the UARTi receive shift register to the UiRB register
Overrun error occurs when the preceding bit of the stop bit of the next data is
received before reading the UiRB register
Framing error occurs when the number of the stop bits set using the STPS bit in the
UiMR register is not detected
Parity error occurs when parity is enabled and the received data does not have the
correct even or odd parity set with the PRY bit in the UiMR register.
Error sum flag becomes 1 when an overrun, framing, or parity error occurs
fj / (16 (m + 1))
when the stop bit is output from the UARTi transmit shift register
(receive operation completed)
fj = f1, f8, f2n
(2)
(1)
m: setting value of the UiBRG register (00h to FFh)
Specification
17. Serial Interfaces (UART0 to UART4)