M3087BFLBGP#U5 Renesas Electronics America, M3087BFLBGP#U5 Datasheet - Page 146

• Manufacturer Part Number: M3087BFLBGP#U5
• Description: IC M32C/87 MCU FLASH 144LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M3087BFLBGP#U5

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IEBus, IrDA, SIO, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 121
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 34x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 144-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
REJ09B0180-0151 Rev.1.51 Jul 31, 2008
Page 122 of 587
11.7
External input to pins INT0 to INT8 generates the INT0 to INT8 interrupt. INT0 to INT5 interrupts can select
either edge sensitive, which the rising/falling edge triggers an interrupt request, or level sensitive, which an input
signal level to the INTi pin (i = 0 to 5) triggers an interrupt request. The INT6 to INT8 interrupts are available only
in the 144-pin package with edge-sensitive triggering.
To use INT0 to INT5 interrupts with edge sensitive, set the LVS bit in the INTiIC register to 0 (edge sensitive), and
select a rising edge, falling edge, or both edges using the POL bit in the INTiIC register and the IFSRi bit in the
IFSR register. When the IFSRi bit is set to 1 (both edges), set the corresponding POL bit to 0 (falling edge). When
the selected edge is detected at the INTi pin, the corresponding IR bit becomes 1.
To use INT0 to INT5 interrupts with level sensitive, set the LVS bit to 1 (level sensitive) and select either “L” level
or “H” level using the POL bit. Also, set the IFSRi bit to 0 (one edge). While the selected level is detected at the
INTi pin, the IR bit becomes 1 and remains 1. Therefore, the interrupt requests are generated repeatedly as long as
the selected level is detected at the INTi pin. When the input signal is changed to the inactive level, the IR bit
becomes 0 by the interrupt request acknowledgement or writing a 0 by a program.
Interrupts can be enabled or disabled using bits ILVL2 to ILVL0 in the INTiIC register.
To use INT6 to INT8 interrupts with edge sensitive, select a rising edge or falling edge by the IFSRj bit (j = 10 to
12) in the IFSRA register. Interrupts can be enabled or disabled using the INTiE bit in the IIOkIE register (k = 9 to
11) and bits ILVL2 to ILVL0 in the IIOkIC register.
Refer to 11.11 Intelligent I/O Interrupts, CAN Interrupts, UART5 and UART6 Transmit/Receive Interrupts,
and INT6 to INT8 Interrupts for details.
Figure 11.11 shows INTi interrupt setting procedures (i = 0 to 5). Figure 11.12 shows INTi interrupt setting
procedures (i = 6 to 8). Figure 11.13 shows the IFSR register and Figure 11.14 shows IFSRA register.
INT Interrupt
11. Interrupts