M3087BFLBGP#U5 Renesas Electronics America, M3087BFLBGP#U5 Datasheet - Page 480

• Manufacturer Part Number: M3087BFLBGP#U5
• Description: IC M32C/87 MCU FLASH 144LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M3087BFLBGP#U5

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IEBus, IrDA, SIO, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 121
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 34x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 144-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
REJ09B0180-0151 Rev.1.51 Jul 31, 2008
Page 456 of 587
Table 23.6
CANij interrupt source
CANi message slot k
receive operation
completed
CANi message slot k
transmit operation
completed
CANi bus error detected
CANi error-passive state
entered
CANi bus-off state
entered
23.4.2.2
When the INTSEL bit is set to 1 (output CAN interrupt request individually), the following three types of
CANij interrupt sources output an interrupt request individually.
Table 23.6 lists interrupt sources and the corresponding interrupt registers (when INTSEL bit is set to 1). Figure
23.43 shows a CANij interrupt block diagram (when INTSEL bit is set to 1).
When a CANij interrupt request is generated, the interrupt status bit (the corresponding bit in the CiSISTR
register or CiEISTR register) becomes 1 (interrupt requested). And then, if the interrupt mask bit (the
corresponding bit in the CiSIMKR register or CiEIMKR register) is set to 1 (interrupt request enabled), the
corresponding intelligent I/O interrupt request bit becomes 1 (interrupt requested).
NOTES:
•
•
•
1. The SISk bits in the CiSISTR register are not cleared to 0 automatically when an interrupt request is
2. The bits in the CiEISTR register are not cleared to 0 automatically when an interrupt request is
When CANi message slot k transmit operation is completed, CANi0 interrupt request is generated.
When CANi message slot k receive operation is completed, CANi1 interrupt request is generated.
When CANi error (bus error detected, error-passive state entered, and bus-off state entered) occurs, CANi2
interrupt request is generated.
acknowledged. Set each bit to 0 by program. If the SISk bit remains 1, the CANi0R or CANi1R bit in the
IIOnIR register (n = 9, 10 when i = 0, n = 0, 1 when i = 1) still becomes 1 (interrupt requested) when a
CANi transmit/receive interrupt request is generated.
acknowledged. Set each bit to 0 by program. While any of enabled status bits remains 1, the CANi2R bit
does not become 1 (interrupt requested) when a CANi error (bus error detected, error-passive state
entered, and bus-off state entered) interrupt request is generated.
When the INTSEL Bit is Set to 1
Interrupt Sources and Interrupt Registers (When INTSEL Bit is Set to 1)
Interrupt status bit
0: interrupt not
1: interrupt requested
SISk bit in the
CiSISTR register
BEIS bit in the
CiEISTR register
EPIS bit in the
CiEISTR register
BOIS bit in the
CiEISTR register
requested
CANij Interrupt
Interrupt mask bit
0: interrupt request
1: interrupt request
SIMk bit in the
CiSIMKR register
BEIM bit in the
CiEIMKR register
EPIM bit in the
CiEIMKR register
BOIM bit in the
CiEIMKR register
disabled
enabled
(output CAN interrupt request individually)
Intelligent I/O interrupt
request
0: interrupt not requested
1: interrupt requested
When i = 0,
CAN00R bit in the IIO9IR
register
When i = 1,
CAN10R bit in the IIO0IR
register
When i = 0,
CAN01R bit in the
IIO10IR register
When i = 1,
CAN11R bit in the IIO1IR
register
When i = 0,
CAN02R bit in the
IIO11IR register
When i = 1,
CAN12R bit in the IIO5IR
register
Intelligent I/O interrupt
23. CAN Module