M3087BFLBGP#U5 Renesas Electronics America, M3087BFLBGP#U5 Datasheet - Page 441

• Manufacturer Part Number: M3087BFLBGP#U5
• Description: IC M32C/87 MCU FLASH 144LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M3087BFLBGP#U5

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IEBus, IrDA, SIO, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 121
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 34x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 144-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
REJ09B0180-0151 Rev.1.51 Jul 31, 2008
Page 417 of 587
Figure 23.10
Figure 23.11
23.1.8
b15
CANi Time Stamp Register (i = 0, 1)
The CiTSR register is a 16-bit counter. Bits TSPRE1 and TSPRE0 in the CiCTLR0 register determine the CAN
bus bit clock divided by 1, 2, 3, or 4 as the count source.
When a transmit or receive operation is completed, the value of the CiTSR register is automatically stored into
the message slot.
In loopback mode, the value of the CiTSR register is stored into the data frame receive message slot or remote
frame receive message slot when a receive operation is completed, if the corresponding message slot is
available to store the message. The value of the CiTSR register is not stored when a transmit operation is
completed in loopback mode.
The CiTSR register starts a counter increment when both the RESET1 and RESET0 bits in the CiCTLR0
register are set to 0 (CAN module is out of reset).
The CiTSR register becomes 0000h in the following timings:
NOTE:
Setting range of each segment
CAN bit time = 8Tq to 25Tq
SS = 1Tq
PTS = 1Tq to 8Tq
PBS1 = 2Tq to 8Tq
PBS2 = 2Tq to 8Tq
SJW = 1Tq to 4Tq
1. The value is obtained by setting the SLEEP bit in the CiSLPR register to 1 (sleep mode exited) after reset and supplying the clock
•
•
•
At the next count timing after the CiTSR register becomes FFFFh.
When both the RESET1 and RESET0 bits are set to 1 (CAN module is reset) by a program.
When the TSRESET bit in the CiCTLR0 register is set to 1 (CiTSR register reset) by a program.
to the CAN module.
b8
CANi Time Stamp Register (CiTSR Register) (i = 0, 1)
SS
b7
CAN bus bit clock =
Bit Timing Diagram
C0TSR and C1TSR Registers
b0
Value of time stamp
Symbol
C0TSR
C1TSR
PTS
Condition of PBS1 and PBS2:
PBS1
CAN bit time
≥
1
PBS2
CAN Bit Time
≥
SJW
Address
0209h - 0208h
0289h - 0288h
Function
PBS1
Sampling point
SJW
PBS2
After Reset
0000h
0000h
SJW
23. CAN Module
(1)
RW
RO