M3087BFLBGP#U5 Renesas Electronics America, M3087BFLBGP#U5 Datasheet - Page 403

• Manufacturer Part Number: M3087BFLBGP#U5
• Description: IC M32C/87 MCU FLASH 144LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M3087BFLBGP#U5

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IEBus, IrDA, SIO, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 121
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 34x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 144-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M32C/87 Group (M32C/87, M32C/87A, M32C/87B) 22. Intelligent I/O (Group 0 and 1 Communication Function)
REJ09B0180-0151 Rev.1.51 Jul 31, 2008
Page 379 of 587
22.4.1
Table 22.14
Table 22.15
NOTE:
Data format
Serial clock
Transmit and receive
start condition
Interrupt request
generation timing
Error detection
Selectable function
Full-duplex clock synchronous serial communication is allowed in this mode. f8, f2n, or external clock can be
selected as the group 0 serial clock. f8, f2n, the clock generated in channel 3, or external clock can be selected as
the group 1 serial clock. Table 22.14 lists specifications of groups 0 and 1 clock synchronous mode. Table 22.15
and 22.16 list clock settings. Table 22.17 lists pin settings. Figures 22.47 to 22.49 show register setting. Figure
22.50 shows an example of a transmit and receive operation.
f8
f2
Input to ISCLK0 pin
1. Bits CNT3 to CNT0 in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15).
(1)
Serial Clock
Item
Clock Synchronous Mode (Groups 0 and 1)
Clock Synchronous Mode Specifications (Groups 0 and 1)
Clock Settings (Group 0)
Data length: 8 bits long
Refer to the Tables 22.15 and 22.16
Select serial clock and set registers GiMR and GiERC (i = 0, 1). Then wait for one or more
serial clock cycles before all of the following conditions are met to start the transmit/receive
operation.
If transmit-only operation is performed, the RE bit setting is not required.
Transmit interrupt (The IRS bit in the GiMR register selects one of the following)
Receive interrupt
• LSB first or MSB first
• ISTXDi and ISRXDi I/O polarity invert
• Overrun error
Overrun error occurs when the 7th bit of the next data is received before reading the GiRB
register. If an overrun error occurs, a read from the GiRB register returns an undefined
value. The OER bit is updated when the data is transferred from the receive shift register to
the GiRB register every time a receive operation is completed.
The SIOiTR bit in IIO1IR or IIO3IR register becomes 1 (interrupt requested) when a transmit
interrupt request is generated (Refer to Figure 11.18).
The SIOiRR bit in IIO1IR or IIO2IR register becomes 1 (interrupt requested) when a receive
interrupt request is generated (Refer to Figure 11.18).
•The TE bit in the GiCR register is set to 1 (transmit operation enabled)
•The TI bit in the GiCR register is set to 0 (data in the GiTB register)
•The RE bit in the GiCR register is set to 1 (receive operation enabled)
•When IRS is set to 0 (no data in the GiTB register):
•When IRS is set to 1 (transmit operation completed):
•When data is transferred from the receive shift register to the GiRB register (receive
Data is transmitted and received from either bit 0 or bit 7.
The level output from the ISTXDi pin and the level applied to the ISRXDi pin are inverted.
When data is transferred from the GiTB register to the transmit shift register (transmit
operation started)
When data transmit operation from the transmit shift register is completed
operation completed)
G0MR Register
CKDIR Bit
0
0
1
Bits CCS1 and CCS0
CCS Register
Specification
11b
10b
−