M3087BFLBGP#U5 Renesas Electronics America, M3087BFLBGP#U5 Datasheet - Page 380

• Manufacturer Part Number: M3087BFLBGP#U5
• Description: IC M32C/87 MCU FLASH 144LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M3087BFLBGP#U5

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IEBus, IrDA, SIO, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 121
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 34x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 144-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
REJ09B0180-0151 Rev.1.51 Jul 31, 2008
Page 356 of 587
22.3.2
Table 22.8
Waveform generation channel
OUTCi_ j pin
Output waveform
Waveform output start condition
Waveform output stop condition
Interrupt request generation timing An interrupt request is generated at the second clock cycle after the base timer
Selectable function
Output level from the OUTCi_j pin is inverted every time the base timer value matches the GiPOj register value
(i = 1, 2; j = 0 to 7).
Table 22.8 lists specifications of phase-delayed waveform output mode. Figure 22.28 shows an example of
phase-delayed waveform output mode operation.
Phase-Delayed Waveform Output Mode (Group 1 and Group 2)
Item
Phase-Delayed Waveform Output Mode Specifications
Group 1 and 2: channels 0 to 7
Pulse output
• Base timer is not reset:
• Base timer is reset when base timer value matches the GiPO0 register value:
Set both the BTS bit in the GiBCR1 register and the IFEj bit in the GiFE register
to 1
Set either the BTS or IFEj bit to 0
value matches the GiPOj register value.
• Initial value set function:
• Inverted output function:
The POijR bit in the IIOkIR register (k = 0 to 11) becomes 1 (interrupt requested)
when an interrupt request is generated.
Cycle:
“H” and “L” widths:
Cycle:
“H” and “L” widths:
(See Figure 11.18 IIO0IR to IIO11IR Registers)
-Bits UD1 and UD0 in G1BCR1 register are set to 00b (counter increment
mode)
-Bits UD1 and UD0 in G1BCR1 register are set to 00b (counter increment mode)
Set the initial output level when waveform output is started (determined by the
IVL bit in the GiPOCRj register)
Output the inverted waveform level (determined by the INV bit in the GiPOCRj
register)
p: setting value of the GiPO0 register (0001h to FFFDh)
If GiPOq register value (q = 1 to 7) (0000h to FFFFh) ≥ p + 2, the output level
is not inverted
65536 × 2
2 (p + 2)
65536
p + 2
fBTi
fBTi
fBTi
fBTi
22. Intelligent I/O (Waveform Generation Function)
Specification