M3087BFLBGP#U5 Renesas Electronics America, M3087BFLBGP#U5 Datasheet - Page 286

• Manufacturer Part Number: M3087BFLBGP#U5
• Description: IC M32C/87 MCU FLASH 144LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M3087BFLBGP#U5

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IEBus, IrDA, SIO, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 121
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 34x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 144-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
REJ09B0180-0151 Rev.1.51 Jul 31, 2008
Page 262 of 587
Figure 17.31
Table 17.18
SCLKDIV bit in the
A
B
Trigger signal input
UiSMR register
Set the SU1HIM bit in the UiSMR2 register (i = 0 to 4) and the SCLKDIV bit in the UiSMR register to values
shown in Table 17.18, and apply a trigger signal to the CTSi pin. Then, the SCLKSTPB bit becomes 1 and a
transmit and receive operation starts. Either the same clock cycle as the external clock or the external clock
cycle divided by two can be selected for the serial clock.
When the SCLKSTPB bit in the UiC1 register is set to 0, a transmission and reception in progress stops
immediately.
Figure 17.31 shows an example of the clock-divided synchronous function.
from the CLKi pin
i = 0 to 4
to the CTSi pin
External clock
Serial clock
Serial clock
A: When the SCLKDIV bit in the UiSMR register is set to 0, and the SU1HIM bit in the UiSMR2 register is set to 1
B: When the SCLKDIV bit is set to 1, and SU1HIM bit is set to either 0 or 1.
0
0
1
TXDi
TXDi
Clock-Divided Synchronous Function Select
Clock-Divided Synchronous Function
SU1HIM bit in the
UiSMR2 register
1
1
0 or 1
More than 1 clock
2
1
cycle is required
0
1
2
3
3
4
2
4
5
Not synchronized
Same clock cycle as the external clock
External clock cycle divided by 2
Clock-Divided Synchronous Function
5
6
3
6
7
7
8
4
8
5
17. Serial Interfaces (UART0 to UART4)
The clock is stopped by the
SCLKSTPB bit in the UiC1 register
6
7
8