M3087BFLBGP#U5 Renesas Electronics America, M3087BFLBGP#U5 Datasheet - Page 292

• Manufacturer Part Number: M3087BFLBGP#U5
• Description: IC M32C/87 MCU FLASH 144LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M3087BFLBGP#U5

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IEBus, IrDA, SIO, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 121
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 34x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 144-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
REJ09B0180-0151 Rev.1.51 Jul 31, 2008
Page 268 of 587
Figure 17.36
17.1.6.2 Formats
17.1.6.2.1 Direct Format
17.1.6.2.2 Inverse Format
(1) Direct format
(2) Inverse format
i = 0 to 4
When data is transmitted, data set in the UiTB register (i = 0 to 4) is transmitted with even parity, starting from
D0
determined with even parity.
Set the bits as follows to transmit or receive in the direct format.
When data is transmitted, values set in the UiTB register are logically inverted. The data with the inverted
values is transmitted with odd parity, starting from D7. When data is received, received data is logically
inverted to be stored into the UiRB register, starting from D7. A parity error is determined with odd parity.
Set the bits as follows to transmit or receive in the inverse format.
•
•
•
•
•
•
•
•
.
When data is received, received data is stored into the UiRB register, starting from D0. A parity error is
Set the PRYE bit in the UiMR register to 1 (parity enabled).
Set the PRY bit in the UiMR register to 1 (even parity).
Set the UFORM bit in the UiC0 register to 0 (LSB first).
Set the UiLCH bit in the UiC1 register to 0 (not inverted).
Set the PRYE bit to 1 (parity enabled).
Set the PRY bit to 0 (odd parity).
Set the UFORM bit to 1 (MSB first).
Set the UiLCH bit to 1 (inverted).
TXDi
TXDi
"H"
"H"
"L"
"L"
SIM Interface Formats
ST
ST
D0
D7
D6
D1
D2
D5
D3
D4
D4
D3
D5
D2
17. Serial Interfaces (UART0 to UART4)
D1
D6
D7
D0
P
P
P: Even parity
P: Odd parity
ST: Start bit
SP: Stop bit
SP
SP