M3087BFLBGP#U5 Renesas Electronics America, M3087BFLBGP#U5 Datasheet - Page 424

• Manufacturer Part Number: M3087BFLBGP#U5
• Description: IC M32C/87 MCU FLASH 144LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M3087BFLBGP#U5

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IEBus, IrDA, SIO, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 121
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 34x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 144-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
REJ09B0180-0151 Rev.1.51 Jul 31, 2008
Page 400 of 587
P6_4
P7_0
P7_1
P9_1
P9_2
P13_4 ISTXD2 Output G2POCR0
P13_5 ISRXD2 Input
P13_6 ISCLK2 Input
Figure 22.61 Transmit/Receive Operation in Variable Clock Synchronous Mode (Group 2)
Port
Table 22.27 Pin Settings in Variable Data Length Clock Synchronous Mode (Group 2)
NOTES:
Serial clock generated with
(1)
(1)
the channel 2 waveform
1. The P7_0 and P7_1 are the N-channel open drain output ports.
2. Set the PD9 or PS3 register immediately after the PRC2 bit in the PRCR register is set to 1 (write enable). Do
3. Set registers PS0, PS1, PS3, and PS7 after setting the other registers.
4. Set bits MOD2 to MOD0 in the corresponding register to 111b (use communication function output).
ISCLK2 Input
ISCLK2 Output G2POCR1
ISTXD2 Output G2POCR0
ISRXD2 Input
ISRXD2 Input
ISTXD2 Output G2POCR0
ISCLK2 Output G2POCR1
not generate an interrupt or a DMA or DMACII transfer between these two instructions.
generation function
Function
ISRXD2
ISTXD2
ISCLK2
−
−
−
−
−
Registers
G2POCR0
G2POCR1
"H"
"H"
"H"
"H"
"L"
"L"
"L"
"L"
(4)
Write data to the
G2TB register
(8-bit data)
IPS6 = 0
−
−
IPS5 and
IPS4 = 00b
IPS5 and
IPS4 = 01b
−
−
IPS5 and
IPS4 =10b
IPS6 = 1
−
Register
IPS
b0
b0
PD6_4 = 0
−
−
PD7_1 = 0
PD9_1 = 0
−
−
PD13_5 = 0 −
PD13_6 = 0 −
−
Registers
PD9, PD13
PD6, PD7,
b1
b1
Write data to the
G2TB register
(4-bit data)
b2
b2
(2)
22. Intelligent I/O (Group 2 Communication Function)
−
−
PSD1_0 = 0 PSC_0 = 1 PSL1_0 = 0 PS1_0 = 1
−
−
−
−
−
Register
PSD1
b6
b6
Transfer to the
G2RB register
Bit Setting
b7
b7
−
−
−
−
−
−
−
−
−
Register
(b8)
(b8)
b0
b0
PSC
(b9)
(b9)
b1
b1
−
PSL0_4 = 1 PS0_4 = 1
−
−
PSL3_2 = 1 PS3_2 = 1
PSL7_4 = 0 PS7_4 = 1
−
−
PSL7_6 = 0 PS7_6 = 0
(b10)
(b10)
Registers
b2
b2
Transfer to the
G2RB register
PSL0,
PSL1,
PSL3,
PSL7
(b11)
(b11)
b3
b3
PS0_4 = 0
PS1_1 = 0
PS3_1 = 0
PS7_5 = 0
PS7_6 = 0
Registers
PS0, PS1
PS3, PS7
(2)(3)