M3087BFLBGP#U5 Renesas Electronics America, M3087BFLBGP#U5 Datasheet - Page 208

• Manufacturer Part Number: M3087BFLBGP#U5
• Description: IC M32C/87 MCU FLASH 144LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M3087BFLBGP#U5

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IEBus, IrDA, SIO, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 121
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 34x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 144-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
REJ09B0180-0151 Rev.1.51 Jul 31, 2008
Page 184 of 587
15.2
Figure 15.21
TBiIN
Timer B contains the following three modes. Bits TMOD1 and TMOD0 in the TBiMR register (i = 0 to 5)
determine which mode is used.
Figure 15.21 shows a block diagram of timer B. Figures 15.22 to 15.26 show the registers associated with timer B.
Table 15.8 shows TBiIN pin settings (i = 0 to 5).
TBj overflow
•
•
•
i= 0 to 5
j = i - 1, except j = 2 if i = 0, j = 5 if i = 3.
NOTES:
TCK1 and TCK0, TMOD1 and TMOD0: Bits in the TBiMR register
TBiS: Bit in the TABSR register or the TBSR register
Timer mode: The timer counts the internal count source.
Event counter mode: The timer counts overflows/underflows of another timer, or the external pulses.
Pulse period measurement mode, pulse width measurement mode: The timer measures the pulse period or
pulse width of the external signal.
f2n
fC32
f1
f8
1. Bits CNT3 to CNT0 in the TCSPR register select no division (n = 0) or
2. Overflow signal or underflow signal.
Polarity switching
Clock source select
and edge pulse
Timer B
(1)
divide-by-2n (n = 1 to 15).
00
01
10
11
TCK1 and TCK0
(2)
Timer B Block Diagram
1
0
TCK1
TMOD1 and TMOD0
00: Timer mode
10: Pulse period and pulse
01: Event counter mode
width measurement mode
TBiS
Counter reset circuit
TBi
Timer B0
Timer B1
Timer B2
Timer B3
Timer B4
Timer B5
High-order bits of data bus
Low-order bits of data bus
Addresses
0351h
0353h
0355h
0311h
0313h
0315h
Reload register
8 low-order
bits
Counter
0350h
0352h
0354h
0310h
0312h
0314h
TBj
Timer B2
Timer B0
Timer B1
Timer B5
Timer B3
Timer B4
8 high-order
bits
15. Timer B