M3087BFLBGP#U5 Renesas Electronics America, M3087BFLBGP#U5 Datasheet - Page 387

• Manufacturer Part Number: M3087BFLBGP#U5
• Description: IC M32C/87 MCU FLASH 144LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M3087BFLBGP#U5

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IEBus, IrDA, SIO, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 121
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 34x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 144-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
REJ09B0180-0151 Rev.1.51 Jul 31, 2008
Page 363 of 587
Figure 22.32
(1) When the base timer is not reset
(2) When the base timer is reset by matching the G2PO0 register
Base timer 2
Count source of
base timer
Base timer value
Read value from
the G2BT register
G2POi register
RTPi bit in the
G2RTP register
OUTC2_i pin
PO2iR bit in the
IIOkIR register
i = 0 to 7; k = 3, 5 to 11
The above applies under the following conditions:
- Bits RST2 to RST0 in the G2BCR1 register are set to 000b (base timer is not reset by matching the G2PO0 register)
- In the G2POCRj register, the IVL bit is set to 0 ("L" output) and the RLD bit is set to 1 (reload when the base timer is reset)
Base timer 2
Count source of
base timer
Base timer value
Read value from
the G2BT register
G2POi register
RTPi bit in the
G2RTP register
OUTC2_i pin
PO2iR bit in the
IIOkIR register
i = 1 to 7; k = 3, 5, 7 to 11
m, n: Setting value of the G2POi register (0000h to FFFFh); p: Setting value of the G2PO0 register (0001h to FFFDh)
The above applies under the following conditions:
- Bits RST2 to RST0 in the G2BCR1 register are set to 010b (base timer is reset by matching the G2PO0 register)
- In the G2POCRi register, the IVL bit is set to 0 ("L" output) and the RLD bit is set to 1 (reload when the base timer is reset)
- m < n < p + 2
Real-Time Port Output Mode Operation
FFFFh
0000h
0000h
"H"
"H"
"L"
"L"
1
0
1
0
p+1
m
m
n
Match
Match
m
m
m, n: Setting value of the G2POj register (0000h to FFFFh)
m
m
m
m
m+1
1
m+1
1
m+1
m+1
p
p
FFFF 0000
p+1
FFFF 0000
p+1
Set to 0 by a program
Set to 0 by a program
Reset
0000
65536 + n - m
0000
p + 2 + n - m
22. Intelligent I/O (Waveform Generation Function)
fBT2
fBT2
n
n
0
n
0
Match
n
n
Match
n+1
n
n+1
n
n+1
n+1
p
p
FFFF 0000
p+1
FFFF 0000
p+1
Reset
0000
0000
1
1