M3087BFLBGP#U5 Renesas Electronics America, M3087BFLBGP#U5 Datasheet - Page 246

• Manufacturer Part Number: M3087BFLBGP#U5
• Description: IC M32C/87 MCU FLASH 144LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M3087BFLBGP#U5

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IEBus, IrDA, SIO, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 121
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 34x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 144-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
REJ09B0180-0151 Rev.1.51 Jul 31, 2008
Page 222 of 587
Figure 17.8
UARTi Baud Rate Register
UARTi Transmit/Receive Control Register 1 (i = 0 to 4)
b7
b7 b6 b5 b4
NOTES:
NOTES:
1. Read-modify-write instructions cannot be used to set the UiBRG register. Refer to Usage Notes for details.
2. Set the UiBRG register after setting bits CLK1 and CLK0 in the UiC0 register.
0
1. The UiLCH bit is enabled when bits SMD2 to SMD0 in the UiMR register are set to 001b (clock synchronous mode), 100b
2. Set bits SMD2 to SMD0 before setting the UiERE bit.
3. When the UiRRM bit is set to 1, set the CKDIR bit in the UiMR register to 1 (external clock) and also disable the RTS function.
(UART mode, 7-bit data length), or 101b (UART mode, 8-bit data length). Set the UiLCH bit to 0 when bits SMD2 to SMD0 are
set to 010b (I
b3
b2
U0BRG to U4BRG Registers, U0C1 to U4C1 Registers
b1
b0
b0
2
C mode) or 110b (UART mode, 9-bit data length).
If the setting value is n ,
the UiBRG register divides a count source by n +1
Bit Symbol
SCLKSTPB
UiRRM
UiLCH
UiERE
UilRS
Symbol
U0BRG to U2BRG
U3BRG, U4BRG
Symbol
U0C1 to U2C1
U3C1, U4C1
RE
TE
RI
TI
Transmit enable bit
UiTB register empty flag
Receive enable bit
Receive complete flag
UARTi transmit interrupt source
select bit
Continuous receive mode
enable bit
Data logic select bit
Special mode 3
Special mode 4
Clock-divided synchronous
stop bit
Error signal output enable bit
(1, 2)
(i = 0 to 4)
Bit Name
Function
(1)
Address
0369h, 02E9h, 0339h
0329h, 02F9h
Address
036Dh, 02EDh, 033Dh
032Dh, 02FDh
(2)
0: Transmit operation disabled
1: Transmit operation enabled
0: Data in the UiTB register
1: No data in the UiTB register
0: Receive operation disabled
1: Receive operation enabled
0: No Data in the UiRB register
1: Data in the UiRB register
0: No data in the UiTB register (TI = 1)
1: Transmit operation is completed (TXEPT = 1)
0: Continuous receive mode disabled
1: Continuous receive mode enabled
0: Not inverted
1: Inverted
0: Synchronization stopped
1: Synchronization started
0: Not output
1: Output
17. Serial Interfaces (UART0 to UART4)
Function
Setting Range
00h to FFh
(3)
After Reset
Undefined
Undefined
After Reset
0000 0010b
0000 0010b
WO
RW
RW
RW
RO
RW
RO
RW
RW
RW
RW