M3087BFLBGP#U5 Renesas Electronics America, M3087BFLBGP#U5 Datasheet - Page 415

• Manufacturer Part Number: M3087BFLBGP#U5
• Description: IC M32C/87 MCU FLASH 144LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M3087BFLBGP#U5

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IEBus, IrDA, SIO, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 121
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 34x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 144-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M32C/87 Group (M32C/87, M32C/87A, M32C/87B) 22. Intelligent I/O (Group 0 and 1 Communication Function)
REJ09B0180-0151 Rev.1.51 Jul 31, 2008
Page 391 of 587
Table 22.24
NOTE:
i = 0,1
CCS
G1BCR0
G1BCR1
G1POCR0
G1POCR1
G1PO0
G1PO1
G1FS
G1FE
GiMR
GiCR
GiEMR
GiETC
GiERC
GiIRF
GiCMP0 and
GiCMP1
GiCMP2
GiCMP3
GiMSK0 and
GiMSK1
GiTCRC
GiRCRC
G1TB
GiTO
GiRI
G1RB
1. These register settings are required when bits CCS3 and CCS2 in the CCS register are set to 00b (clock
Register
(1)
(1)
generated with the waveform generation function).
(1)
(1)
(1)
(1)
(1)
(1)
Register Settings in HDLC Data Processing Mode (Groups 0 and 1)
CCS1 and CCS0
CCS3 and CCS2
BCK1 and BCK0
DIV4 to DIV0
IT
−
−
−
−
−
FSC1 and FSC0
IFE1 and IFE0
GMD1 and GMD0
CKDIR
UFORM
IRS
TE
TXEPT
TI
RE
RI
−
TCRCE
TBSF1
CMP2E to CMP0E
CMP3E
RCRCE
RSHTE
RBSF1
IRF3 to IRF0
−
−
−
−
−
−
−
−
−
−
Bit
Select transfer clock.
Select transfer clock.
Select count source.
Select count source divide ratio.
Select the base timer interrupt generation timing.
Set to 0001 0010b.
Set to 0000 0000b.
Set to 0000 0000b.
Set baud rate.
Set the timing of the rising edge of the transfer clock.
Timing of the falling edge (“H” width of the transfer clock) is fixed.
Setting value of the G1PO1 register ≤ setting value of the G1PO0 register
Set to 00b.
Set to 11b.
Set to 11b.
Set to 0.
Set to 0.
Select a transmit interrupt source.
Set to 1 to enable a transmit operation (HDLC frame data generation from
source data).
Transmit shift register empty flag
GiTB register empty flag
Set to 1 to enable a receive operation (source data generation from HDLC
frame data).
Receive completion flag
Set to 1111 0110b.
Set to 1 (CRC calculation is performed when HDLC frame data is generated
from source data).
Set to 1 (“0” is inserted when HDLC frame data is generated).
Select whether or not the GiDR register and GiCMPj register (j = 0 to 2) are
compared.
Set to 1.
Set to 1 (CRC calculation is performed when source data is generated from
HDLC frame data).
When source data is generated, set to 1.
Set to 1 (“0” is deleted when source data is generated).
Select an interrupt source.
Write FEh to detect an abort sequence.
Set data to be compared.
Write 7Eh.
Write 01h to detect an abort sequence.
The CRC code, which is calculated when generating HDLC frame data from
source data, can be read.
The CRC code, which is calculated when generating source data from HDLC
frame data, can be read.
Used to generate HDLC frame data. Write source data.
Used to generate HDLC frame data. HDLC frame data, which is generated
from source data, can be read.
Used to generate source data. Write HDLC frame data.
Used to generate source data. Source data, which is generated from HDLC
frame data, can be read.
Function