M3087BFLBGP#U5 Renesas Electronics America, M3087BFLBGP#U5 Datasheet - Page 264

• Manufacturer Part Number: M3087BFLBGP#U5
• Description: IC M32C/87 MCU FLASH 144LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M3087BFLBGP#U5

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IEBus, IrDA, SIO, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 121
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 34x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 144-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
REJ09B0180-0151 Rev.1.51 Jul 31, 2008
Page 240 of 587
Figure 17.21
Figure 17.22
17.1.2.3 Serial Data Logic Inverse
17.1.2.4 TXD and RXD I/O Polarity Inverse
(1) When the UiLCH bit in the UiC1 register (i = 0 to 4) is set to 0 (not inverted)
(2) When the UiLCH bit is set to 1 (inverted)
(2) When the IOPOL bit is set to 1 (inverted)
(1) When the IOPOL bit in the UiMR register (i = 0 to 4) is set to 0 (not inverted)
When the UiLCH bit in the UiC1 register is set to 1 (inverted), data logic written in the UiTB register is inverted
for transmit operation. A read from the UiRB register returns the inverted logic of receive data. This function
can be used when data length is 7 bits or 8 bits long. Figure 17.21 shows an example of serial data logic inverse
operation.
The level output from the TXD pin and the level applied to the RXD pin are inverted with this function. When
the IOPOL bit in the UiMR register (i = 0 to 4) is set to 1 (inverted), all the input/output data levels, including
the start bit, stop bit and parity bit, are inverted. Figure 17.22 shows TXD and RXD I/O polarity inverse.
(not inverted)
The above applies under the following conditions:
The above applies under the following conditions:
(not inverted)
(not inverted)
(inverted)
- UiC0 register: UFORM bit = 0 (LSB first)
- UiMR register: STPS bit = 0 (1 stop bit)
- UiC0 register: UFORM bit = 0 (LSB first)
- UiMR register: STPS bit = 0 (1 stop bit)
(inverted)
(inverted)
TXDi
TXDi
RXDi
RXDi
TXDi
TXDi
Serial Data Logic Inverse
TXD and RXD I/O Polarity Inverse
"H"
"H"
"L"
"L"
"H"
"H"
"H"
"H"
"L"
"L"
"L"
"L"
PRYE bit = 1 (parity enabled)
PRYE bit = 1 (parity enabled).
ST
ST
ST
ST
ST
ST
D0
D0
D0
D0
D0
D0
D1
D1
D1
D1
D1
D1
D2
D2
D2
D2
D2
D2
D3
D3
D3
D3
D3
D3
D4
D4
D4
D4
D4
D4
D5
D5
D5
D5
D5
D5
17. Serial Interfaces (UART0 to UART4)
D6
D6
D6
D6
D6
D6
D7
D7
D7
D7
D7
D7
P
P
P
P
P
P
ST: Start bit
P: Parity bit
SP: Stop bit
SP
SP
SP
SP
SP
SP