M3087BFLBGP#U5 Renesas Electronics America, M3087BFLBGP#U5 Datasheet - Page 152

• Manufacturer Part Number: M3087BFLBGP#U5
• Description: IC M32C/87 MCU FLASH 144LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M3087BFLBGP#U5

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IEBus, IrDA, SIO, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 121
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 34x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 144-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
REJ09B0180-0151 Rev.1.51 Jul 31, 2008
Page 128 of 587
11.11 Intelligent I/O Interrupts, CAN Interrupts, UART5 and UART6 Transmit/
Figure 11.17
The intelligent I/O interrupts are shared by CAN interrupt, INT6 to INT8 interrupts, UART5 and UART6 transmit/
receive interrupt. A logical sum of interrupt request signals from individual peripheral functions is used to generate
an interrupt.
Figure 11.17 shows a block diagram of the intelligent I/O interrupts. Figure 11.18 shows the IIOiIR (i = 0 to 11)
register. Figure 11.19 shows the IIOiIE register.
Interrupt request
Interrupt request
Interrupt request
"0" write signal
"0" write signal
"0" write signal
i = 0 to 11, j = 0 to 5
NOTES:
Receive Interrupts, and INT6 to INT8 Interrupts
1. Bits 1 to 7 in the IIOiIR register do not automatically become 0 when the interrupt request is acknowledged. Set to 0 by
2. Do not change the interrupt enable bit (bits 1 to 7 in the IIOiIE register) and IRLT bit in the IIOiIE register simultaneously.
to bit 1
to bit2
to bit7
signal
signal
signal
a program.
Intelligent I/O Interrupt Block Diagram
IIOiIE register
IIOiIR register
IRLT
bit 1
bit 2
bit 7
bit 1
bit 2
bit 7
S Q
R
S Q
R
S Q
R
(2)
(1)
0
1
0
1
0
1
When this signal changes from
0 to 1, the IR bit in the IIOiIC
(CANjIC) register becomes 1.
IR bit in the IIOiIC
(CANjIC) register
D Q
R
IR bit is cleared to 0 by an interrupt
request acknowledgement or by
writing a 0 to the IR bit.
To the interrupt priority
level decision circuit
11. Interrupts