M3087BFLBGP#U5 Renesas Electronics America, M3087BFLBGP#U5 Datasheet - Page 178

• Manufacturer Part Number: M3087BFLBGP#U5
• Description: IC M32C/87 MCU FLASH 144LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M3087BFLBGP#U5

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IEBus, IrDA, SIO, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 121
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 34x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 144-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
REJ09B0180-0151 Rev.1.51 Jul 31, 2008
Page 154 of 587
Figure 14.3
Chain transfer
End-of-
Transfer
Interrupt
DMAC II index
Transfer data
Table 14.2
b15
Transfer Mode (MOD)
NOTES:
1. MOD must be located in the RAM.
2. When the MULT bit is set to 0, bits 6 to 4 function as bits OPER, BRST, and INTE. When the MULT bit is set to 1, bits 6 to 4
function as bits CNT2 to CNT0.
b8 b7
Not used
Not used
COUNT
8 bytes
SADR
DADR
MOD
DMACII Index Configuration in Transfer Mode
MOD
b0
Memory-to-Memory Transfer/
Immediate Data Transfer
Not used
COUNT
12 bytes
CADR0
CADR1
SADR
DADR
Used
Bit Symbol
MOD
(b14-b8)
CNT0
CNT1
CNT2
OPER/
CHAIN
BRST/
UPDS
UPDD
MULT
INTE/
SIZE
IMM
(1)
−
(2)
(2)
(2)
Not used
12 bytes
COUNT
DADR
IADR0
IADR1
Transfer unit select bit
Transfer data select bit
Transfer source direction
select bit
Transfer destination
direction select bit
Calculation transfer
function select bit
Burst transfer select bit
End-of-transfer interrupt
select bit
Chain transfer
select bit
Unimplemented.
Write 0. Read as undefined value.
Multiple transfer
select bit
SADR
Used
MOD
Bit Name
16 bytes
COUNT
CADR0
CADR1
IADR0
IADR1
SADR
DADR
Used
MOD
Used
0: 8 bits
1: 16 bits
0: Immediate data
1: Memory
0: Fixed address
1: Incremented address
0: Fixed address
1: Incremented address
0: Not used
1: Used
0: Single transfer
1: Burst transfer
0: Interrupt not used
1: Interrupt used
0: Multiple transfer not
0: Chain transfer not
1: Chain transfer used
Not used
Not used
10 bytes
COUNT
OADR
DADR
used
SADR
MOD
used
(MULT = 0)
Function
14 bytes
Not used
COUNT
CADR0
CADR1
OADR
SADR
DADR
MOD
Used
Calculation Transfer
b6 b5 b4
0 0 0: Do not set to this
0 0 1: Once
0 1 0: Twice
1 1 0: 6 times
1 1 1: 7 times
Set to 1
Set to 0
1: Multiple transfer used
:
:
Not used
14 bytes
COUNT
OADR
IADR0
IADR1
SADR
DADR
MOD
Used
value
(MULT = 1)
Function
18 bytes
COUNT
CADR0
CADR1
OADR
IADR0
IADR1
SADR
DADR
MOD
Used
Used
Cannot used
Cannot used
max. 32 bytes
(when i = 7)
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Transfer
i = 1 to 7
Multiple
COUNT
SADR1
DADR1
−
SADRi
DADRi
14. DMACII
MOD